Patents Assigned to STMicroelectronics International N.V.
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Patent number: 11923855Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.Type: GrantFiled: September 13, 2022Date of Patent: March 5, 2024Assignee: STMicroelectronics International N.V.Inventors: Manoj Kumar Tiwari, Saiyid Mohammad Irshad Rizvi
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Publication number: 20240071429Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.Type: ApplicationFiled: August 14, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Nitin CHAWLA, Promod KUMAR, Kedar Janardan DHORI, Manuj AYODHYAWASI
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Publication number: 20240071546Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.Type: ApplicationFiled: July 28, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Hitesh CHAWLA, Tanuj KUMAR, Bhupender SINGH, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Publication number: 20240071480Abstract: Disclosed herein is an electronic device, including a plurality of row decoders. Each row decoder includes decoder logic generating an initial word line signal and word line driver circuitry generating an inverse word line signal at an intermediate node from the initial word line signal, and generating a word line signal at a word line node from the inverse word line signal. A word line underdrive p-channel transistor has a source coupled to the intermediate node, a drain coupled to a word line underdrive sink, and a gate controlled based upon the inverse word line signal. Negative bias generation circuitry generates the negative bias voltage at a gate of the word line underdrive p-channel transistor when the initial word line signal is at a logic high, and couples the gate of the word line underdrive p-channel transistor to ground when the initial word line signal is at a logic low.Type: ApplicationFiled: August 8, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Ashish KUMAR, Dipti ARYA
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Publication number: 20240071439Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.Type: ApplicationFiled: August 14, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Nitin CHAWLA, Promod KUMAR, Kedar Janardan DHORI, Manuj AYODHYAWASI
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Publication number: 20240069096Abstract: An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input/output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.Type: ApplicationFiled: July 31, 2023Publication date: February 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Bhupender SINGH, Hitesh CHAWLA, Tanuj KUMAR, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
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Patent number: 11914499Abstract: A trace-data preparation circuit including a filtering circuit to receive traced memory-write data and a First In First Out buffer coupled with the filtering circuit to receive selected memory-write data filtered by the filtering circuit. The trace-data preparation circuit further including a data compression circuit to provide packaging data to a packaging circuit that groups the selected memory-write data.Type: GrantFiled: October 29, 2021Date of Patent: February 27, 2024Assignees: STMicroelectronics Application GMBH, STMicroelectronics S.r.l., STMicroelectronics International N.V.Inventors: Avneep Kumar Goyal, Thomas Szurmant, Misaele Marletti, Alessandro Daolio
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Patent number: 11909410Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.Type: GrantFiled: November 7, 2022Date of Patent: February 20, 2024Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Sharad Gupta
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Patent number: 11908528Abstract: An integrated circuit includes a charge pump. The charge pump includes a plurality of charge pump stages and a plurality of switches. The switches can operated to selectively couple the charge pump stages in various arrangements of series and parallel connections based on a currently selected operational mode of the charge pump. The charge pump assists in performing read and write operations for a memory array of the integrated circuit.Type: GrantFiled: November 15, 2021Date of Patent: February 20, 2024Assignee: STMicroelectronics International N.V.Inventors: Vikas Rana, Arpit Vijayvergia
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Publication number: 20240056091Abstract: An integrated circuit includes a plurality of ADC channels. During a calibration process of the ADC channels, the integrated circuit utilizes derivative filters to calculate a phase difference between the ADC channels. During a calibration process, the integrated circuit utilizes clock phase alignment circuits to align the phases of the ADC channels based on the outputs of the derivative filters.Type: ApplicationFiled: August 1, 2023Publication date: February 15, 2024Applicant: STMicroelectronics International N.V.Inventors: Ankur BAL, Jeet Narayan TIWARI
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Patent number: 11900240Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.Type: GrantFiled: September 16, 2020Date of Patent: February 13, 2024Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin Chawla, Giuseppe Desoli, Manuj Ayodhyawasi, Thomas Boesch, Surinder Pal Singh
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Patent number: 11901865Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.Type: GrantFiled: September 13, 2022Date of Patent: February 13, 2024Assignee: STMicroelectronics International N.V.Inventors: Anand Kumar, Nitin Jain
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Patent number: 11901919Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.Type: GrantFiled: April 18, 2022Date of Patent: February 13, 2024Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Abhishek Jain, Sharad Gupta
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Patent number: 11901900Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a main PMOS branch that charges an intermediate node of the Schmitt trigger responsive to voltage transitions at the input node. The Schmitt trigger includes a charging assistance circuit that helps to rapidly charge the intermediate node of the Schmitt trigger. The charging assistance circuit includes a parallel PMOS branch in parallel with the main PMOS branch.Type: GrantFiled: June 17, 2022Date of Patent: February 13, 2024Assignee: STMicroelectronics International N.V.Inventors: Kailash Kumar, Manoj Kumar
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Publication number: 20240045589Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin CHAWLA, Giuseppe DESOLI, Anuj GROVER, Thomas BOESCH, Surinder Pal SINGH, Manuj AYODHYAWASI
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Publication number: 20240045458Abstract: Provided are techniques for detecting a short circuit fault at an output of a regulator and protecting the regulator from the short circuit fault. An error amplifier receives a reference voltage and a feedback voltage and compares comparing the reference voltage with the feedback voltage for driving a power transistor of the regulator. A modification stage compares an output voltage of the voltage regulator with a fault reference voltage and in response to determining that the output voltage of the voltage regulator is less than the fault reference voltage, drives the power transistor using an internal node of the error amplifier by changing states of a first switch and a second switch and supplies the reference voltage to both the first and second inputs of the error amplifier by changing states of a third switch and a fourth switch.Type: ApplicationFiled: July 21, 2023Publication date: February 8, 2024Applicant: STMicroelectronics International N.V.Inventors: Zubair KHAN, Sandeep KAUSHIK
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Patent number: 11892505Abstract: A processing system includes: main and shadow processing cores configured to operate in lockstep based on a core clock. The main processing core includes a main processing core and a main debug circuit. The shadow processing core includes a shadow functional core and a shadow debug circuit. A redundancy checker circuit is configured to assert an alarm signal when a discrepancy between outputs from the main and shadow functional cores is detected. A debug bus synchronizer circuit is configured to receive input debug data in synchrony with a debug clock, and provide synchronized debug data in synchrony with the core clock to a debug bus based on the input debug data, where the main and shadow debug circuits are configured to receive the synchronized debug data in synchrony with the core clock from the debug bus, and where the debug clock is asynchronous with respect to the core clock.Type: GrantFiled: September 15, 2022Date of Patent: February 6, 2024Assignee: STMicroelectronics International N.V.Inventors: Avneep Kumar Goyal, Anubhav Arora
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Publication number: 20240039537Abstract: The present disclosure is directed to a high-voltage fault protection for an interface circuit. The interface circuit is transmitting data signals through an output driver to an external circuit coupled to a PAD contact. The output driver includes pull-up and pull-down drivers. The pull-up driver includes two series PMOS coupled between a voltage supply and the PAD. The pull-down driver includes two series NMOS coupled between the PAD and a ground node. A first safe signal is coupled to one PMOS. A first circuit scheme is designed to generate the first safe signal to be low-logical level voltage when the PAD voltage is lower than a threshold, while being high-logical level voltage when the PAD voltage is higher than the threshold. A second circuit scheme is designed to control one of the series NMOS to be in OFF state when the PAD voltage is higher than the threshold.Type: ApplicationFiled: July 20, 2023Publication date: February 1, 2024Applicant: STMicroelectronics International N.V.Inventors: Manoj KUMAR, Paras GARG, Saiyid Mohammad Irshad RIZVI
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Publication number: 20240039545Abstract: Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.Type: ApplicationFiled: July 7, 2023Publication date: February 1, 2024Applicant: STMicroelectronics International N.V.Inventors: Rupesh SINGH, Ankur BAL
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Patent number: 11885849Abstract: A method can be used for supervising the operation of a machine powered with electric current. The method includes operating the machine in a normal operation mode, repeatedly performing a learning phase for learning the normal operation machine of the machine to create a knowledge base, autonomously switching from the learning phase into a supervision phase when the knowledge base is considered to have been created, and repeatedly performing the supervision phase.Type: GrantFiled: September 23, 2021Date of Patent: January 30, 2024Assignee: STMicroelectronics International N.V.Inventors: He Huang, Francois De Grimaudet De Rochebouet