Abstract: An optical module includes a fast-axis mirror that scans a laser beam along a fast-axis, a magnification mirror set formed by three discrete mirrors shaped to magnify the laser beam as it is scanned along the fast-axis and reflect the laser beam after magnification toward a slow-axis mirror that scans the laser beam along the slow-axis, and an Offner mirror relay that receives the laser beam as it is scanned along the slow-axis and reflects the laser beam out an exit aperture. The laser beam as output from the exit aperture is received at an input diffractive grating of a diffractive waveguide, with a user's eye being positioned adjacent an output diffractive grating of the waveguide such that the user's eye views ambient light entering the waveguide from objects within the user's field of view as well as light from the laser beam as it exits the output diffractive grating.

Abstract: A circuit includes a transistor, with a resonant tank coupled between a DC supply node and a first conduction terminal of the transistor. A gate driver generates a gate drive signal for biasing a control terminal of the transistor to cause it to conduct current through the resonant tank. Control circuitry monitors a voltage across the transistor to determine that the transistor is an overvoltage condition if that voltage exceeds a threshold, and monitors a current through the transistor to determine that the transistor is an overcurrent condition if that current exceeds a threshold. If overvoltage is determined, the control circuitry causes the gate driver to pull up the gate drive signal. If overcurrent is determined, the control circuitry causes the gate driver to pull down the gate drive signal. If either overvoltage or overcurrent is present, a pulse width of the gate drive signal is reduced.

Abstract: A charge pump circuit includes a boost capacitor driven by a first clock signal and a bootstrap capacitor driven by a second clock signal. The first and second clock signals have different duty cycles, with the duty cycle of the second clock signal being smaller than the duty cycle of the first clock signal. An input transistor is coupled between an input node and a boost node coupled to the boost capacitor. The control terminal of the input transistor is coupled to the bootstrap capacitor. A bootstrap transistor coupled between the boost node and the control terminal of the input transistor is driven by a logical inverse of the first clock signal.

Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits.

Abstract: This application discloses systems, devices, and methods for indoor navigation and tracking with a mesh network. In one aspect, a navigation device includes a receiver configured to receive a locational signal from a node network. The locational signal identifies a respective node of the node network, and the node network is distributed throughout a physical space. The navigation device includes a memory storing a program and a processor in communication with the receiver and configured to execute the program to calculate a position of the navigation device from the identity of the respective node, determine a routing instruction from the position of the navigation device to a destination based on the position of the navigation device and a known mapping of the node network in the physical space, and update the position of the navigation device and the routing instruction as the navigation device moves through the physical space.

Abstract: A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.

Abstract: The present disclosure is directed to a lead frame design that includes a copper alloy base material coated with an electroplated copper layer, a precious metal, and an adhesion promotion compound. The layers compensate for scratches or surface irregularities in the base material while promoting adhesion from the lead frame to the conductive connectors, and to the encapsulant by coupling them to different layers of a multilayer coating on the lead frame. The first layer of the multilayer coating is a soft electroplated copper to smooth the surface of the base material. The second layer of the multilayer coating is a thin precious metal to facilitate a mechanical coupling between leads of the lead frame and conductive connectors. The third layer of the multilayer coating is the adhesion promotion compound for facilitating a mechanical coupling to an encapsulant around the lead frame.

Abstract: A read-modify-write operation is performed, within a single cycle of a clock signal, by: decoding an address to select a word line of a memory; applying a word line signal at a first voltage level to the selected word line; reading a current data word from a data word location in the memory; reducing the word line signal from the first voltage level to the second voltage level; performing a mathematical modify operation internally within the memory on the current data word to generate a modified data word; increasing the word line signal from the second voltage level to the first voltage level; and writing the modified data word back to the location in the memory.

Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.

Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.

Abstract: A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.

Abstract: A voltage controlled oscillator (VCO) has a VCO core and a tuning bank. The tuning bank includes first and second tuning capacitors. A main switch is coupled between the first and second tuning capacitors. The tuning bank also includes control switches that receive a control signal to selectively activate the tuning bank. The main switch receives a level-shifted control signal to activate the tuning bank.

Abstract: A Multiple Accumulate (MAC) hardware accelerator includes a plurality of multipliers. The plurality of multipliers multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input. A result is generated based on the multiplication of the digit-serial input by the parallel input. An accelerator framework may include multiple MAC hardware accelerators, and may be used to implement a convolutional neural network. The MAC hardware accelerators may multiple an input weight by an input feature by sequentially multiplying individual digits of the input weight by the input feature.

Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

Abstract: An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serial izer without utilizing a deserializer.

Abstract: A leadframe including a metal oxide layer on at least a portion of the leadframe are disclosed. More specifically, leadframes with a metal layer and a metal oxide layer formed on one or more leads before a tin finish plating layer is formed are described. The layers of metal and metal oxide between the one or more leads and the tin finish plating layer reduce the formation of tin whiskers, thus reducing the likelihood of shorting and improving the overall reliability of the package structure and device produced.

Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.

Abstract: An active compensation circuit for compensating the stability of a regulator is provided. The active compensation circuit presents an equivalent capacitance and an equivalent resistance and compensates stability of system using the equivalent capacitance and the equivalent resistance. The regulator includes a power transistor that receives a driving signal and channelize the required current to the Ips driven by this block. The regulator's stability is compensated using the active compensation circuit to provide an accurate output voltage without significantly compromising the accuracy (load regulation) and area of the system.