Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.

Abstract: An orientation sensor for use with an image sensor is provided, which includes at least two polarizers with different orientations and associated photodetectors and a signal processing unit. The orientation sensor can be incorporated in a digital camera. When the camera is exposed to daylight, which is polarized, the relative outputs from the differently oriented polarizers can be compared to record the orientation of the camera. This orientation can be stored with the image data so that a user does not have to manually change the orientation of an image on an image display device.

Abstract: A card reader reads data stored on a card. A contact signal is produced whose state is indicative of the presence or absence of electrical contact between the card and the card reader. A high state indicates the presence of electrical contact and a low state indicates the absence of electrical contact. Upon insertion of the card into the card reader, vibrations and other mechanical perturbations of the card cause the state of the contact signal to fluctuate rapidly between high and low states. The state of the contact signal is periodically sampled for a predetermined period of time and the number of samples for which the contact signal was high are counted. If the number of high samples exceeds a threshold then stable electrical contact is deemed to have been established between the card and the card reader and a system reset is performed.

Abstract: A resource management system including a plurality of requester elements competing to access a resource through an arbiter element that controls access to the resource by the requester elements. A requester element having a buffer unit and first and second counters, which are compared to determine if a request having an identified priority type is in the buffer unit.

Abstract: A method for processing an instruction word in a data processing system, the instruction word comprising a plurality of instruction bit positions, each bit position corresponding to an instruction actions, and a status of the bit at an instruction bit position indicating whether the instruction action corresponding to that bit position should be performed; the method comprising: forming a plurality of single action words, each single action word corresponding to one of the instruction actions and having a bit set at the bit position corresponding to that instruction actions and all its other bits un-set; forming a common action word having bits set at the bit positions corresponding to the instruction actions of any of the single action words and all its other bits un-set; comparing the instruction word and the common action word, and if the instruction word and the common action word have no bits set in common terminating processing of the instruction, and otherwise: repeating for successive single action wo

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals comprises an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. Control signals broadcast with the television signals include control words and common keys. Entitlement messages are received in encrypted form, encrypted according to a secret key unique to each semiconductor integrated circuit. The input interface is connected to a decryption circuit whereby the only manner of providing the common keys to the circuit are in encrypted form encrypted according to the secret key. Due to the monolithic nature of the circuit, no secrets are exposed and the system is secure. Alternatively, the entitlement messages are encrypted for decryption with the common keys and a unique ID stored in the circuit is compared with an ID in a received entitlement message. Only if the received and stored IDs match can the rights be stored and used.

Abstract: A system for controlling communications between a host and a target, the system having a data input for receiving a data signal, a clock input for receiving a clock signal, an oversampling circuit for sampling a received data signal and generating a control signal to control processing of the received data signal based at least in part on samples of the received data signal.

Abstract: Disclosed are systems for loading an unaligned word from a specified unaligned word address in a memory, the unaligned word comprising a plurality of indexed portions crossing a word boundry, a method of operating the system comprising: loading a first aligned word commencing at an aligned word address rounded from the specified unaligned word address; identifying an index representing the location of the unaligned word address relative to the aligned word address; loading a second aligned word commencing at an aligned word address rounded from a second unaligned word address; and combining indexed portions of the first and second alinged words using the indentified index to construct the unaligned word.

Abstract: The invention provides circuitry for carrying out a square root operation. The circuitry utilizes iteration circuitry for carrying out a plurality of iterations. The iteration circuitry includes a circuit for calculating a root multiple, the root multiple being a multiple of a current quotient value. The root multiple is used by the iteration circuitry to modify a current remainder.

Abstract: A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.

Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.

Abstract: A semiconductor integrated circuit includes a hardware mechanism arranged to ensure that associations between instructions and data are enforced so that a processor cannot fetch data from an instruction that is not authorised to do so. A Memory Protection Unit stores entries comprising instructions and associated data memory ranges. A hardware arrangement impairs the operation of the circuit if the CPU attempts to make a data fetch from an instruction that is outside the range associated with data in a Memory Protection Unit. Such functioning may be by issuing a chip reset. The Memory Protection Unit may be implemented in a Memory Management Unit having an extension so as to store a validity flag. The validity flag may only be set by a secure process such as the CPU well entrusted code or by a separate trusted hardware source. In this way, an operating system may function as normal referring to the Memory Management Unit as necessary, but security may be enforced through hardware.

Abstract: A memory access system including a memory in which data is organized in pages, each page holding a sequence of data elements; means for receiving a requested address including a requested page address and a requested data element address; logic for accessing a current page from the memory using a current page address; logic for reading out data elements of the current page in the sequence in which they are held in memory; logic for comparing the requested page address with the current page address and for issuing a memory access request with the requested page address when they are not the same; and logic operable when the requested page address is the same as the current page address for comparing a requested data element address with the current address of a data element being read out and returning the data element when the requested data element address matches the current data element address.

Abstract: A biasing circuit comprising a first switching device having a control terminal, and first and second switching terminals. The first switching terminal being connected to a supply voltage, the second switching terminal being connected through a first resistive element to ground, and the control terminal being supplied by a reference voltage which is determined depending on the mode of operation of the circuit. The circuit further comprising a first branch connected between the control terminal and ground comprising a second resistive element in series with a second switching device. The second switching device forming part of a first current mirror having a second branch for effecting a generated bias value. During a normal mode of operation the reference voltage is dependant on the generated bias value, whereas during a standby mode of operation the reference voltage is connected to a low potential.

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, sample reducer combines samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators without sample reduction. The same correlators are thereby used to increase acquisition speed.

Abstract: A method and system for validating speculative load operations. The system identifies speculative load operations that might be executed in a code sequence and after translating the virtual address of the speculative load to a physical address, a speculative load control unit is used to define a plurality of memory regions and has means for checking whether the physical addresses lie within at least one of said defined memory regions. In this way, the control unit allows the mapping of large physical page size to RAM devices and the extra address space is filtered off by the control unit so that speculative loads are not carried out in unknown regions.

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, a memory arrangement comprising two circulating shift registers circulates samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators. The same correlators are thereby used to increase acquisition speed.

Abstract: An integrated circuit comprising: a plurality of portions, each portion including test control circuitry; at least one test input arranged to receive test signals; and a multiplexer between the at least one test input and the test control circuitry, the multiplexer having a least one control input whereby the multiplexer is controllable to direct test signals to one of the plurality of portions.

Abstract: Circuitry is provided for performing a non-arithmetic operation in relation to at least one number. The circuitry includes a first part for carrying out the non-arithmetic operation in relation to the at least one number, the first part providing a result. A second part is arranged to identify at least one characteristic of the at least one number and to provide an output and correction circuitry for providing, if necessary, a correct result in dependence on the output of the second part, wherein said first and second parts are arranged to operate in parallel.

Abstract: A method for performing a reordering operation on a matrix of input data values, the method comprising: loading the data values into a computer store by forming a plurality of data strings, each data string comprising a plurality of data sub-strings and each data sub-string representing at least one of the data values, and storing each data string in a register of the computer store in which its sub-strings are not individually addressable; and performing a series of data reordering steps operating on one or more of said data strings to reorder said data values; the reordering operation being a scan-wise reordering operation.