Abstract: A video decoding circuit comprising: a first video data processor; a second video data processor; and a connection connecting the first video data processor and the second data processor; wherein the first video data processor is arranged to receive a first signal comprising encoded video data, process the first signal to provide a second signal and output the second signal. The first video data processor being arranged to process the first signal dependent on at least part of the received first signal. The second video data processor is arranged to receive at least a part of the second signal, process the at least a part of the second signal to provide a third signal, and output the third signal, the second and third signals comprising a decoded video image stream. The second video data processor is arranged to process the at least part of the second signal dependent on at least part of the at least part of second signal.

Abstract: A method of locating packet identifiers held in respective memory locations in a memory, the method comprising receiving a plurality of packets, each packet including a packet identifier, searching said memory locations in a sequence to compare an incoming packet identifier with packet identifiers stored in the memory until a match is found, incrementing one of a set of counters associated respectively with the memory locations, said incremented counter being the one associated with the memory location where the match packet identifier is held, and reading values of each of the counters and using said values to determine the sequence in which the memory locations are searched for subsequent incoming packet identifiers.

Abstract: Circuitry for testing and implementing a distributed tristate bus, the circuitry being configured in the testing mode, when a first signal is supplied to a first enable input and a test enable signal is operative, the cascade circuitry outputs a cascade out signal to the cascade input via the cascade output, causing the second cascade circuitry to disable the enable input of the second tristate cell, thereby to reduce the possibility of contention of the data bus during scan testing.

Abstract: A memory stores data in an encrypted form. A modifiable register stores a memory address, a0, defining a boundary separating the memory into two regions. The lower region stores data encrypted using a key B, and the upper region stores data encrypted using a different key A. Data stored on the boundary address is encrypted using key A. Accordingly, when data is read from a memory address a, key A is used to decrypt the data if a?a0, and key B is used if a<a0. However, when data is written to a memory address a, then key A is used to encrypt the data if a?a0+1, key B is used if a<a0+1. When data is written to the boundary address, a0, the position of the boundary is caused to increase by one unit.

Abstract: A portion of data is obfuscated by performing a bitwise XOR function between bits of the data portion and bits of a mask. The mask is generated based on the memory address of the data portion. A bitfield representing the memory address of the data portion is split into subset bitfields. Each subset then forms the input of a corresponding primary randomizing unit. Each primary randomizing unit is arranged to generate an output bitfield that appears to be randomly correlated with the input, but which may be determined from the input if certain secret information is known. The output of the primary randomizing units is input into a series of secondary randomizing units. Each secondary randomizing unit is arranged to input at least one bit of the output of every primary randomizing unit. The output of the secondary randomizing units are then combined by concatenation to form a data mask.

Abstract: A filter is arranged to selectively block or allow a data access command from an initiator according to whether the initiator is secure or insecure and whether a data source or destination being accessed is privileged or unprivileged. The data access command contains an identification of the initiator from which the data access command originated and an identification of the data source or destination being accessed. The security filter compares the initiator identification and data source or destination identification contained within the data access command with a list of those initiators defined as secure and a list of those data sources or destinations which are defined as unprivileged. The filter then blocks or allows the data access command signal according to a set of rules.

Abstract: A method of linking a plurality of object files to generate an executable program, the method comprises identifying in the object files at least one routine to be locked into a cache when the program is executed, locating said routine at a set of memory addresses which man onto a set of cache locations and introducing into the executable program gaps at other sets of memory addresses which map onto the same set of cache locations.

Abstract: A method of linking a plurality of object code modules to form an executable program, each object code module having section data, a set of relocation instructions and one or more symbols, each symbol having a plurality of attributes associated therewith, wherein the relocation instructions include a data retrieval instruction having a symbol field identifying a symbol and an attribute field identifying a symbol attribute associated with the identified symbol to be retrieved, the method including reading at least one relocation instruction from the set of relocation instructions and where the relocation instruction is a data retrieval instruction, determining the symbol identified by the symbol field and retrieving one of the plurality of symbol attributes associated with the symbol in dependence on the contents of the symbol attributes field of the instruction.

Abstract: A device for locating a DES key value that corresponds to a packet identification (PID) contained at a variable possible location which comprises part only of a 32-bit packet header. A table stored in memory contains for each DES key: (i) a packet header having 32 bits with a PID of either 12, 9 or 8 bits contained at a defined location and with zero values elsewhere, and (ii) a mask value also having 32 bits with ones contained at the said defined location of the PID and zeros elsewhere. The table is divided into regions for respective packet format types. An incoming packet header at an input is combined with a first one of the mask values from the table to provide a combined value that consists of the value held in the input packet header at the defined location and zeros elsewhere. This combined value is compared with the corresponding packet header stored in the table. When they are not equal, the combining and comparison is repeated for the next row of the table.

Abstract: A method of arranging an integrated circuit to correct for hold time errors comprises fixing the position of existing cells in a design, determining hold time errors required to be corrected and placing buffer cells in spaces in the existing design. By placing buffer cells in spaces in the existing design, rather than moving cells in the existing design, the hold time can be corrected without changing the critical path.

Abstract: A mute switch including a field effect transistor receiving a mute control signal at its gate for selectively supplying an audio signal from an input node to an output node. A bipolar transistor is connected between the input node and the FET for reducing the voltage level of the audio signal prior to its application to the input node, and a further bipolar transistor is connected between the FET and the output node for raising the voltage level of the audio signal prior to its application to the output node. This serves to maintain the DC bias level of the audio output signal independently of the status of the mute control signal.

Abstract: Circuitry for carrying out an arithmetic operation requiring a plurality of iterations, such as division or square root operations, utilizes N sets of iteration circuitry arranged one after the other so that at least one of the sets of iteration circuitry receives an output from a preceding one of the sets of iteration circuitry. Each of the sets of iteration circuitry includes at least one adder part, wherein a full adder is provided by at least one part in one of the sets of iteration circuitry and a second part in a succeeding one of the sets of iteration circuitry.

Abstract: A method distributes personalized circuits to one or more parties. The method distributes a generic circuit to each party, encrypts a unique personalization value using a secret encryption key, and transmits each encrypted personalization value to the corresponding party. Each party then stores the encrypted personalization value in their circuit. The stored encrypted personalization value allows a piece of software to be properly executed by the circuit. A semiconductor integrated circuit is arranged to execute a piece of software that inputs a personalization value as an input parameter. The circuit comprises a personalization memory arranged to store an encrypted personalization value; a key memory for storing a decryption key; a control unit comprising a cryptographic circuit arranged to decrypt the encrypted personalization value using the decryption key; and a processor arranged to receive the decrypted personalization value and execute the software using the decrypted personalization value.

Abstract: A field programmable device is disclosed, including a plurality of logic blocks; a plurality of connections connecting the logic blocks; configuration circuitry for outputting configuration data for programming the field programmable device, the configuration circuitry providing at least one pair of outputs; and error detection circuitry for comparing the outputs to determine if there has been a configuration error.

Abstract: A graphic processor having an index processing unit for pre-processing a list of vertices making up a three-dimensional image. The method of pre-processing comprising the following steps. First, decomposing the three-dimensional image into a plurality of primitive elements each defined by a set of vertices, each vertex comprising vertex information stored in a vertex storage area and addressable by a vertex index. Then receiving said vertex indices and creating a set of unique indices identifying a batch of vertices and loading only the vertices corresponding to said unique indices into the vertex storage area. Finally creating transformed primitive elements from transformed vertex information addressed in the vertex storage area using the unique indices.

Abstract: The invention provides circuitry for carrying out a square root operation and a division operation. The circuitry utilizes common iteration circuitry for carrying out a plurality of iterations and means for identifying if an square root operation or a division operation is to be performed. The iteration circuitry is controlled in accordance with whether a square root or division operation is to be performed.

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test data, wherein the test data is clocked in a plurality of time slots, with test data for different ones of the plurality of portions being allocated to different time slots.

Abstract: The present invention is directed to methods for verifying adequate synchronization of signals that cross clock environments. According to one exemplary method, a circuit under design includes a plurality of functional elements and a plurality of clock environments, and has one or more signals passing from one clock environment to another therein. The method includes the steps of (i) modelling at least one of the functional elements to have an unknown state as an output for a predetermined time after a timing event of a clock signal, (ii) simulating the circuit, and (iii) determining which functional element is a synchronizer to thereby identify if there is a synchronization problem for a signal passing from one clock environment to another.

Abstract: A method of forming an executable program from a plurality of object code modules where each object code module includes a plurality of relocation instructions having at least one information output relocation with a field indicating information to be output. The method includes reading a relocation instruction from one of the object code modules and, when the read relocation instruction is an information output relocation, displaying the information indicated in the field in a human readable form.

Abstract: This patent describes a method of compiling a computer program from a sequence of computer instructions including a plurality of first, set branch, instructions which each identify a target address for a branch and a plurality of associated second, effect branch instructions which each implement a branch to a target address. The method comprising the steps of; reading the computer instructions in blocks; defining a set of target registers associated with each block for holding target addresses for the set branch instructions in that block; defining as a live range of blocks a set of blocks for which a target address of a particular set branch instruction is in a live state; and using the set of target registers and the live range to ensure that target registers holding target addresses in a live state are not available for other uses.