Abstract: The present invention relates to a high voltage output circuit for driving a gray scale flat panel display. The high voltage output circuit eliminates the inaccuracies of prior art output circuits by using a plurality of transistors to eliminate a dead band level within the output circuit. The output circuit is also less expensive than prior art output circuits since a level translator is not required.

Abstract: A high voltage current limiting protection circuit for measurement equipment and measurement probes. The circuit is comprised of a plurality of elements one of which is variable resistance means which are coupled between a first terminal and a second terminal of the circuit for generating a low resistance level to allow a fast response by the measurement equipment to measure current flowing between the two terminals. The variable resistance means generates a high resistance level to limit current flow to a minimum level between the two terminals when a predetermined maximum voltage level across the two terminals is exceeded. Voltage trip point means are coupled to the variable resistance means for setting the predetermined maximum voltage level to trigger the variable resistance means to generate the high resistance level to limit current flow between the two terminals to the minimum level.

Abstract: Method and structure is disclosed for a high-density DMOS transistor with an improved body contact. The improvement comprises a self-aligned structure in combination with a body contact region which overdopes the source region in order to minimize the number of critical photoresist steps. The use of two dielectric spacers obviates the need for a separate contact mask.

Abstract: A high-voltage level translator circuit is disclosed that is suitable for monolithic integration. The level translator circuit comprises serially-connected current sources suitably ratioed so that the gating on of one current source causes a limited voltage rise across the other current source, which is ungated. The circuit is suitable for integration in a junction-isolated monolithic pseudo-complementary CMOS format.

Abstract: Integrated MOS devices with intermediate ion-implanted regions for minimizing device interaction. Several configurations are detailed; they are individually or, in combination, extremely useful in maximizing the density of ROM functions implemented in the integrated circuit format. In particular, one of the embodiments enhances the achievable density in a row-column array used in ROM memories. Used together, the embodiments are especially suited for a ROM of the CMOS genre.

Abstract: This is an improved approach to the operation of an integrated circuit memory, especially of the MOS type. The approach is especially suitable for use with CMOS read-only memories (ROMs). Specific improvements include address-triggered pulse generation, power switching and sharing for individual cells, a pseudo-dynamic approach to achieve quasi-static operation, self-compensating means for both "word" lines and "bit" lines, use of complementary decoding devices for the mutually orthogonal directions in the memory, and an improved output function. Specific circuitry for implementing the above approaches in a CMOS integrated circuit includes an address-triggered pulse generator, a self-tracking reference voltage source derived from both the "word" lines and the "bit" lines, an output stage with a CMOS driver into a bipolar transistor, and a sense amplifier including a capacitor.

Abstract: Improved circuitry for providing a stable reference voltage in complementary transistor circuitry. The circuitry comprises a pair of complementary transistors and a pair of zener diodes interconnected to reduce reference voltage variation with respect to supply voltages.

Abstract: A merged MOS/bipolar structure for high current device applications. Using the same process sequence both an MOS device as a bipolar device are formed in a single semiconductor substrate. Integral input circuitry means couples the input terminals of the individual devices to the composite input terminal to control the relative currents carried by the individual devices as a function of the input signal.

Abstract: This disclosure relates to a high power VMOS semiconductor device and fabrication method therefor. This VMOS semiconductor device uses a doped polysilicon gate electrode in the V groove and an overlying metal electrode located over an insulation layer protecting the doped polysilicon gate electrode. This overlying metal electrode layer covers substantially the entire surface area (except for a small area where electrical contact is made to the doped polysilicon gate electrode) of one surface of the device.

Abstract: A semiconductor device providing improved utilization of semiconductor surface area by enhancing the current carrying capability per unit area. The improvement arises from contouring the surface in the conductive channel region of the device so that the current carrying channel is wider than the plane surface that it occupies. This morphology may be achieved by forming troughs having optional rectangular, "U", or "V" shapes; the troughs run parallel to the conductive channel current flow. The improvement is especially useful for MOS and power MOS transistors, and is applicable to DMOS transistors as well as conventional MOS transistors.

Abstract: Device means for reducing latch-back breakdown thus raising the reverse-biased power capability of a DMOS transistor or the like. A DMOS transistor is an MOS field effect transistor comprising a lightly-doped (usually diffused) body region formed in a drain region; a heavily-doped source region is located in the body region in proximity to the drain. Since such a device structure also exhibits substantial bipolar transistor action, it is prone to latch-back breakdown. Means for reducing latch-back breakdown include providing a distributed diode with a lower breakdown voltage than the DMOS transistor to non-destructively absorb reverse transients or by providing shunt conductance means for the diffused channel region to reduce both the voltage and the voltage gradient in the base of the parasitic bipolar device. These means may be used singly or in combination.

Abstract: A detection circuit particularly adapted as a smoke detector employs a minimum number of components by a CMOS integrated circuit which receives directly the output of a smoke detector on one of the inputs of an input comparator circuit which provides static input protection and a high input impedance by employing thick oxide layer over the gates of the comparator transistors. The CMOS chip also directly supplies operating current for a mechanical or piezoelectric horn. Further features include a clocked low voltage alarm; a buffer stage to permit the interconnection of a number of different detector circuits in common to a single input/output lead; and a visual LED indicator to indicate that the circuit is operating and to provide a visual indication any time the alarm condition for the circuit has been actuated.

Abstract: This disclosure relates to an improved DMOS semiconductor type device which can function both as a DMOS (unipolar) type device and as a bipolar transistor device. The DMOS device has two separated source regions of, for example, N+ conductivity and each of these source regions is surrounded by a P- type region, thus providing a pair of channels between each N+ source region and a common N type drain region located between the P- regions. A gate electrode is disposed over both of the channels and functions to permit electrons from the N+ source regions to flow across the P- channels into the common N type drain region when a proper bias is applied to the gate region. Each of the source regions has its own electrode and a separate electrode is provided to each of the P- regions that surround each of the respective N+ source regions.

Abstract: A detection circuit particularly adapted as a smoke detector employes a minimum number of components by a CMOS integrated circuit which receives directly the output of a smoke detector on one of the inputs of an input comparator circuit which provides static input protection and a high input impedence by employing thick oxide layer over the gates of the comparator transistors. The CMOS chip also directly supplies operating current for a mechanical or piezoelectric horn. Further features include a clocked low voltage alarm; a buffer stage to permit the interconnection of a number of different detector circuits in common to a single input/output lead; and a visual LED indicator to indicate that the circuit is operating and to provide a visual indication any time the alarm condition for the circuit has been actuated.

Abstract: A detection circuit particularly adapted as a smoke detector employs a minimum number of components by a CMOS integrated circuit which receives directly the output of a smoke detector on one of the inputs of an input comparator circuit which provides static input protection and a high input impedance by employing thick oxide layer over the gates of the comparator transistors. The CMOS chip also directly supplies operating current for a mechanical or piezoelectric horn. Further features include a clocked low voltage alarm; a buffer stage to permit the interconnection of a number of different detector circuits in common to a single input/output lead; and a visual LED indicator to indicate that the circuit is operating and to provide a visual indication any time the alarm condition for the circuit has been actuated.

Abstract: This disclosure relates to a high power VMOS semiconductor device and fabrication method therefor. This VMOS semiconductor device uses a doped polysilicon gate electrode in the V groove and an overlying metal electrode located over an insulation layer protecting the doped polysilicon gate electrode. This overlying metal electrode layer covers substantially the entire surface area (except for a small area where electrical contact is made to the doped polysilicon gate electrode) of one surface of the device. Another embodiment discloses the use of a self-aligned metal contact to the source or drain region of the VMOS device between adjacent V grooves.