Abstract: A method is disclosed. The method includes computing a time delay for each path of a plurality of paths of a circuit design and determining a commonality score based on a number of segments that are common between the plurality of paths of the circuit design. The method further includes determining a criticality score based on the time delay for each path of the plurality of paths of the circuit design. The method further includes generating a graphical representation of the plurality of paths, wherein a first dimension of the graphical representation corresponds to the commonality score and wherein a second dimension of the graphical representation corresponds to the criticality score. The method further includes providing the graphical representation of the plurality of paths in a graphical user interface (GUI) to represent the plurality of paths in the circuit design.

Abstract: A method for modelling timing behavior using augmented sensitivity data for physical parameters is disclosed. The method includes acquiring timing library data and sensitivity data for a physical parameter associated with a circuit design, generating a timing behavior model for the circuit design based on the timing library data and sensitivity data for the physical parameter, and storing the timing behavior model. The timing behavior model reduces a difference between a current known best measurement associated with the circuit design and a static timing analysis timing for the circuit design.

Abstract: New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the circuit. A flow of the local circuit simulation of the pre-layout netlist and the post-layout netlist of the same design is presented. A flow of reference or relative or differential circuit simulation of a known design and a new design of the same kind is described. This Abstract is not intended to limit the scope of the claims.

Abstract: A system and method which compensates for phase mixer circuit non-linearities within a clock and data recovery (CDR) system during active operation. The CDR system includes compensation circuitry and phase accumulation circuitry. The compensation circuitry generates a first compensation signal based on a first compensation value. The phase accumulation circuitry receives the first compensation signal and a phase accumulator input update signal. The phase accumulation circuitry combines the first compensation signal with the phase accumulator input update signal to compensate for a first non-linearity within phase mixer (PMI) circuitry.

Abstract: A method for processing a source code file comprises scanning the source code file to identify text lines, and analyzing, via one or more processors, the text lines with a classifier to identify one or more of the text lines that correspond to code construct type information. The code construct type information includes license information. The classifier is trained with sample source code files. The method further comprises generating a subset of the text lines that excludes the one or more of the text lines identified as corresponding to the code construct type information. Further, the method comprises determining first text lines within the subset that correspond to open source code by comparing the subset to a database. The database includes a plurality of text lines associated with open source code.

Abstract: Disclosed herein are system, computer-implemented method, and computer program product (computer-readable storage medium) embodiments for implementing an intelligent DevSecOps workflow. An embodiment includes receiving, by at least one processor, a risk profile associated with a software deployment, and an update related to the software deployment; and evaluating, by the at least one processor, at least one parameter associated with the update, to produce an evaluation result. Additionally, the at least one processor may determine a set of actions in response to the update, based at least in part on the evaluation result, an application dataset corresponding to the software deployment, and a group of specified criteria on which the risk profile is based; or perform at least one action of the set of actions in response to the update, according to some example use cases.

Abstract: A communication device includes controller circuitry and transmitter circuitry. The controller circuitry determines a number of strings of consecutive ones in a data packet, and determines a number of stuffed bytes based on the number of strings of consecutive ones. Further, the controller circuitry schedules a transaction packet to be transmitted within a bus interval based on a determination that a total number of bytes of the transaction packet is less than a number of available bytes in the bus interval. The total number of bytes of the transaction packet is based on a number of payload bytes of the data packet and the number of stuffed bytes. The transmitter circuitry transmits the transaction packet during the bus interval based on the controller circuitry scheduling the transaction packet for transmission.

Abstract: In one aspect, a method includes invoking a signoff tool via a first command from an implementation tool running on a register transfer level (RTL) design, and executing a native command of the signoff tool from within the implementation tool. The native command generates a notification. The method also includes determining whether the RTL design passes a low-power signoff check based on the notification and sending the design for final signoff verification based on the determination that the RTL design passes the low-power signoff checks.

Abstract: A method and system for performing duty-cycle correction (DCC) on a clock signal is provided. The method provides a two-step duty cycle correction. The method can include performing a main DCC of a single-ended clock signal, to generate a duty cycle adjusted single-ended clock signal, wherein a duty cycle of the single-ended clock signal is corrected according to a received duty-cycle continuous control signal and converting the duty cycle adjusted single-ended clock signal to differential clock signals. The method can further include performing a trim DCC by correcting a duty cycle of the differential clock signals according to a duty-cycle trim control signal received and generated in dependence upon duty cycles detected from differential output clock signals to provide error-corrected differential clock signals.

Abstract: A system and method for performing a store to load process includes receiving a first store instruction. The first store instruction includes a first target address, a first mask, and a first data structure. Further, the first target address, the first mask, and the first data structure are stored within a first store buffer location of a store buffer. A first entry identification associated with the first store buffer location is stored within an age buffer. The first data structure is output based on an order of entry identifications within the age buffer.

Abstract: Described is technology for automatically generating a routing for an integrated circuit (IC) design. Information describing pin-pairs of an integrated circuit (IC) design is received. An initial routing of the IC design is determined by (i) defining connected wires between each pin-pair in the set of pin-pairs, and (ii) evaluating a target resistance for the pin-pair over the connected wires, wherein each connected wire is routed with other connected wires. A resistance adjustment is applied to adjust wire resistance of the connected wires of the initial routing. The resistance adjustment can be based on a square routing in response to a wire resistance being below the target resistance; or the resistance adjustment can be based on a multi-layer stacking in response to the wire resistance being above the target resistance. The routing is provided in patterns as generated by the initial routing and the resistance adjustment.

Abstract: Disclosed herein are embodiments including electrical structures that includes a first cell, a first inductor, a first resistor, and a first shunted Josephson junction. The first inductor is connected in series with the first shunted Josephson junction at a first terminal end of the first inductor and a second terminal end of the first inductor is connected to a feed point of the first cell being powered. A first end of the first resistor having connected to ground and a second end being connected to the first shunted Josephson junction at a terminal of the first shunted Josephson junction that is not connected to the first inductor. A source of an electrical current source that is external to the first cell is connected to the first shunted junction and the first resistor at a common point.

Abstract: A system performs static program analysis with artifact reuse. The system identifies artifacts associated with the software program being analyzed. The system processes the identified artifacts for performing static program analysis and transmits either the artifacts or identifiers for the artifacts to a second processing device for performing program analysis. The second processing device receives the artifacts and uses the received identifiers to retrieve the artifacts from a networked storage system. The second device also retrieves stored summaries of previous program analysis from the networked storage system. The program analysis uses the retrieved artifacts to generate work units for static program analysis. The analysis is performed only for those work units that are determined to remain unchanged from previous static program analysis cycles.

Abstract: A method comprising receiving a plurality of signatures representing one or more proprietary files from a vendor generated without disclosure of the proprietary files, each signature corresponding to a segment of a proprietary file. The method further comprising and validating each of the plurality of the signatures, to ensure that the signatures are the proprietary code of the vendor. The method further comprises adding the plurality of the signatures to a global database, the global database used to compare the proprietary data of the vendor to other technology data and taking various action based on the results of the comparison.

Abstract: Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed in sufficient thermal communication with the integrated circuit die so as to derive, from heat generated by the die, a voltage difference across first and second terminals of the thermoelectric generator structure. A powering structure is arranged to help power the integrated circuit, from the voltage difference across the first and second terminals of the thermoelectric generator. The thermoelectric generator can include IC packaging material that is made from thermoelectric semiconductor materials.

Abstract: A system and method corrects single bit errors in a memory by detecting a single bit error with a memory. The memory is accessed via data cache stages of a pipeline. Further, based on detecting the single bit error, the data cache stages of the pipeline are stopped from accepting new transactions. A value associated with each address of the memory is read based on stopping the new transactions from being accepted, and the detected single bit errors within the values are corrected.

Abstract: A method includes extracting information associated with constraints and clock information from a file of a circuit design; determining a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, and performing timing analysis on the partition of the two or more partitions based on the topological cone. The topological cone includes objects associated with the partition of the two or more partitions of the circuit design.

Abstract: Sensor data relating to operating conditions for an integrated circuit are read out through scan chains. Scan tests are run on an integrated circuit containing logic circuits that implement logic functions. The logic circuits are interconnected to form scan chains which are used in running the scan tests. The scan test data resulting from the scan tests is read out from the logic circuits through these scan chains. During the scan tests, sensor blocks capture measurements of the operating conditions for the logic circuits. The operating conditions may include process, voltage and/or temperature conditions, for example. The sensor blocks are also interconnected to form one or more scan chains, and sensor data produced from the captured measurements is read out through these scan chains concurrently with the read out of the scan test data.

Abstract: A method includes receiving a circuit design. The circuit design includes blocks, a clock port, and two or more clock sinks across the blocks. The method further includes determining, by one or more processors, a common clock path between the clock port and the two or more clock sinks across the blocks. Further, the method includes determining a clock latency based on the common clock path.

Abstract: A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.