Abstract: A system and method for performing a store to load process includes receiving a first store instruction. The first store instruction includes a first target address, a first mask, and a first data structure. Further, the first target address, the first mask, and the first data structure are stored within a first store buffer location of a store buffer. A first entry identification associated with the first store buffer location is stored within an age buffer. The first data structure is output based on an order of entry identifications within the age buffer.

Abstract: Described is technology for automatically generating a routing for an integrated circuit (IC) design. Information describing pin-pairs of an integrated circuit (IC) design is received. An initial routing of the IC design is determined by (i) defining connected wires between each pin-pair in the set of pin-pairs, and (ii) evaluating a target resistance for the pin-pair over the connected wires, wherein each connected wire is routed with other connected wires. A resistance adjustment is applied to adjust wire resistance of the connected wires of the initial routing. The resistance adjustment can be based on a square routing in response to a wire resistance being below the target resistance; or the resistance adjustment can be based on a multi-layer stacking in response to the wire resistance being above the target resistance. The routing is provided in patterns as generated by the initial routing and the resistance adjustment.

Abstract: A method comprising receiving a plurality of signatures representing one or more proprietary files from a vendor generated without disclosure of the proprietary files, each signature corresponding to a segment of a proprietary file. The method further comprising and validating each of the plurality of the signatures, to ensure that the signatures are the proprietary code of the vendor. The method further comprises adding the plurality of the signatures to a global database, the global database used to compare the proprietary data of the vendor to other technology data and taking various action based on the results of the comparison.

Abstract: A system performs static program analysis with artifact reuse. The system identifies artifacts associated with the software program being analyzed. The system processes the identified artifacts for performing static program analysis and transmits either the artifacts or identifiers for the artifacts to a second processing device for performing program analysis. The second processing device receives the artifacts and uses the received identifiers to retrieve the artifacts from a networked storage system. The second device also retrieves stored summaries of previous program analysis from the networked storage system. The program analysis uses the retrieved artifacts to generate work units for static program analysis. The analysis is performed only for those work units that are determined to remain unchanged from previous static program analysis cycles.

Abstract: Disclosed herein are embodiments including electrical structures that includes a first cell, a first inductor, a first resistor, and a first shunted Josephson junction. The first inductor is connected in series with the first shunted Josephson junction at a first terminal end of the first inductor and a second terminal end of the first inductor is connected to a feed point of the first cell being powered. A first end of the first resistor having connected to ground and a second end being connected to the first shunted Josephson junction at a terminal of the first shunted Josephson junction that is not connected to the first inductor. A source of an electrical current source that is external to the first cell is connected to the first shunted junction and the first resistor at a common point.

Abstract: Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed in sufficient thermal communication with the integrated circuit die so as to derive, from heat generated by the die, a voltage difference across first and second terminals of the thermoelectric generator structure. A powering structure is arranged to help power the integrated circuit, from the voltage difference across the first and second terminals of the thermoelectric generator. The thermoelectric generator can include IC packaging material that is made from thermoelectric semiconductor materials.

Abstract: A system and method corrects single bit errors in a memory by detecting a single bit error with a memory. The memory is accessed via data cache stages of a pipeline. Further, based on detecting the single bit error, the data cache stages of the pipeline are stopped from accepting new transactions. A value associated with each address of the memory is read based on stopping the new transactions from being accepted, and the detected single bit errors within the values are corrected.

Abstract: A method includes extracting information associated with constraints and clock information from a file of a circuit design; determining a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, and performing timing analysis on the partition of the two or more partitions based on the topological cone. The topological cone includes objects associated with the partition of the two or more partitions of the circuit design.

Abstract: Sensor data relating to operating conditions for an integrated circuit are read out through scan chains. Scan tests are run on an integrated circuit containing logic circuits that implement logic functions. The logic circuits are interconnected to form scan chains which are used in running the scan tests. The scan test data resulting from the scan tests is read out from the logic circuits through these scan chains. During the scan tests, sensor blocks capture measurements of the operating conditions for the logic circuits. The operating conditions may include process, voltage and/or temperature conditions, for example. The sensor blocks are also interconnected to form one or more scan chains, and sensor data produced from the captured measurements is read out through these scan chains concurrently with the read out of the scan test data.

Abstract: A method includes receiving a circuit design. The circuit design includes blocks, a clock port, and two or more clock sinks across the blocks. The method further includes determining, by one or more processors, a common clock path between the clock port and the two or more clock sinks across the blocks. Further, the method includes determining a clock latency based on the common clock path.

Abstract: A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.

Abstract: An example system includes a processor that can receive a queue testing package. The processor can divide a hardware (HW) queue system to be tested into different types of queues. The processor can also generate a test using the different types of queues. The processor can further execute multiple instances of the generated test. The processor can also further compare results of the multiple instances of the test to detect a hardware fault in the hardware queue system.

Abstract: Reset Domain Crossing (RDC) detection and simulation is provided via identifying a plurality of RDCs between flip-flops of a sequence of flip-flops leading to an observation point in a circuit design; classifying each RDC of the plurality of RDCs as one of observable at the observation point or not observable at the observation point based on a reset order applied to the sequence of flip-flops; and outputting a list of the plurality of RDCs classified as observable at the observation point.

Abstract: A method is provided for performing power validation on an integrated circuit (IC) design based on a power assertion specification. The method includes receiving the power assertion specification for the IC design, where the power assertion specification includes a predicted power consumption. Power consumption of the IC design is estimated according to power assertions specified in the power assertion specification. The estimated power consumption is compared against the predicted power consumption included in the power assertion specification. The IC design is determined to be associated with a power assertion failure based on results of the comparing. In response to determining that the IC design is associated with the power assertion failure, the IC design is refined to remedy the power assertion failure.

Abstract: A memory address may be received at an m-way set-associative cache, which may store a set of cache entries. The memory address may be partitioned into a tag, an index, and an offset. The m-way set-associative cache may include a first structure to store a first subset of tag bits corresponding to the set of cache entries and a second structure to store a second subset of tag bits corresponding to the set of cache entries. The index may be used to select a first set of entries from the first structure. A first portion of tag bits of the memory address may be matched with the first set of entries. A cache status may be determined based on matching the first portion of tag bits of the memory address with the first set of entries.

Abstract: In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.

Abstract: A memory cell comprises a pair of cross-coupled inverters as a storage element, a first inverter in the pair of cross-coupled inverters having a first output at a first node, a second inverter in the pair of cross-coupled inverters having a second output at a second node. A first complementary transmission gate includes a first nMOS pass gate and a first pMOS pass gate, connected between the first node and a first bit line. A second complementary transmission gate includes a second nMOS pass gate and a second pMOS pass gate, connected between the second node and a second bit line. A first word line is connected to gate conductors of the first and second nMOS pass gates in the first and second complementary transmission gates. A second word line is connected to gate conductors of the first and second pMOS pass gates in the first and second transmission gates.

Abstract: For each circuit element in a pair of launch and capture paths, a parameter value of the circuit element may be modified by a variation amount that is assigned to a class of circuit elements to which the circuit element belongs. Next, a timing slack may be computed for the pair of launch and capture paths.

Abstract: A method of improving mask data used in fabrication of a semiconductor device includes, in part, setting a threshold value associated with a defect based on stochastic failure rate of the defect, performing a first optimal proximity correction (OPC) of the mask data using nominal values of mask pattern contours, identifying locations within the first OPC mask data where stochastically determined mask pattern contours may lead to the defect, placing check figures on the identified locations to enable measurement of distances between the stochastically determined mask pattern contours, and performing a second OPC of the first OPC mask data so as to cause the measured distances to be greater than the threshold value.

Abstract: A level shifter circuit includes a first current mirror coupled between a power terminal and a ground terminal, a second current mirror coupled between the power terminal and the ground terminal, and a level shifter. The level shifter includes a first transistor coupled to the first current mirror and a second transistor coupled to the second current mirror. The first current mirror and the second current mirror control a state of the first transistor and the second transistor.