Patents Assigned to Synopsys, Inc.
  • Patent number: 11942936
    Abstract: Disclosed herein are embodiments including electrical structures that includes a first cell, a first inductor, a first resistor, and a first shunted Josephson junction. The first inductor is connected in series with the first shunted Josephson junction at a first terminal end of the first inductor and a second terminal end of the first inductor is connected to a feed point of the first cell being powered. A first end of the first resistor having connected to ground and a second end being connected to the first shunted Josephson junction at a terminal of the first shunted Josephson junction that is not connected to the first inductor. A source of an electrical current source that is external to the first cell is connected to the first shunted junction and the first resistor at a common point.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: March 26, 2024
    Assignee: Synopsys, Inc.
    Inventor: Stephen Robert Whiteley
  • Patent number: 11943369
    Abstract: A method comprising receiving a plurality of signatures representing one or more proprietary files from a vendor generated without disclosure of the proprietary files, each signature corresponding to a segment of a proprietary file. The method further comprising and validating each of the plurality of the signatures, to ensure that the signatures are the proprietary code of the vendor. The method further comprises adding the plurality of the signatures to a global database, the global database used to compare the proprietary data of the vendor to other technology data and taking various action based on the results of the comparison.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: March 26, 2024
    Assignee: Synopsys, Inc.
    Inventors: Mikko Einari Varpiola, Craig E. Shinners
  • Patent number: 11937507
    Abstract: Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed in sufficient thermal communication with the integrated circuit die so as to derive, from heat generated by the die, a voltage difference across first and second terminals of the thermoelectric generator structure. A powering structure is arranged to help power the integrated circuit, from the voltage difference across the first and second terminals of the thermoelectric generator. The thermoelectric generator can include IC packaging material that is made from thermoelectric semiconductor materials.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: March 19, 2024
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Jamil Kawa
  • Patent number: 11928024
    Abstract: A system and method corrects single bit errors in a memory by detecting a single bit error with a memory. The memory is accessed via data cache stages of a pipeline. Further, based on detecting the single bit error, the data cache stages of the pipeline are stopped from accepting new transactions. A value associated with each address of the memory is read based on stopping the new transactions from being accepted, and the detected single bit errors within the values are corrected.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: March 12, 2024
    Assignee: Synopsys, Inc.
    Inventor: Karthik Thucanakkenpalayam Sundararajan
  • Patent number: 11922106
    Abstract: A method includes extracting information associated with constraints and clock information from a file of a circuit design; determining a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, and performing timing analysis on the partition of the two or more partitions based on the topological cone. The topological cone includes objects associated with the partition of the two or more partitions of the circuit design.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: March 5, 2024
    Assignee: SYNOPSYS, INC.
    Inventors: Abhishek Nandi, Qiuyang Wu, Yogesh Dilip Save
  • Patent number: 11921160
    Abstract: Sensor data relating to operating conditions for an integrated circuit are read out through scan chains. Scan tests are run on an integrated circuit containing logic circuits that implement logic functions. The logic circuits are interconnected to form scan chains which are used in running the scan tests. The scan test data resulting from the scan tests is read out from the logic circuits through these scan chains. During the scan tests, sensor blocks capture measurements of the operating conditions for the logic circuits. The operating conditions may include process, voltage and/or temperature conditions, for example. The sensor blocks are also interconnected to form one or more scan chains, and sensor data produced from the captured measurements is read out through these scan chains concurrently with the read out of the scan test data.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: March 5, 2024
    Assignee: Synopsys, Inc.
    Inventors: Bartosz Grzegorz Gajda, Anubhav Sinha
  • Patent number: 11914939
    Abstract: A method includes receiving a circuit design. The circuit design includes blocks, a clock port, and two or more clock sinks across the blocks. The method further includes determining, by one or more processors, a common clock path between the clock port and the two or more clock sinks across the blocks. Further, the method includes determining a clock latency based on the common clock path.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: February 27, 2024
    Assignee: Synopsys, Inc.
    Inventors: Prashant Gupta, Shibaji Banerjee, Sivakumar Arulanantham
  • Patent number: 11914306
    Abstract: A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: February 27, 2024
    Assignee: Synopsys, Inc.
    Inventors: Erik A. Verduijn, Ulrich Karl Klostermann, Ulrich Welling, Jiuzhou Tang, Hans-Jürgen Stock
  • Patent number: 11907088
    Abstract: An example system includes a processor that can receive a queue testing package. The processor can divide a hardware (HW) queue system to be tested into different types of queues. The processor can also generate a test using the different types of queues. The processor can further execute multiple instances of the generated test. The processor can also further compare results of the multiple instances of the test to detect a hardware fault in the hardware queue system.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: February 20, 2024
    Assignee: Synopsys, Inc.
    Inventors: Hillel Mendelson, Tom Kolan, Hagai Hadad, Shay Aviv
  • Patent number: 11907631
    Abstract: Reset Domain Crossing (RDC) detection and simulation is provided via identifying a plurality of RDCs between flip-flops of a sequence of flip-flops leading to an observation point in a circuit design; classifying each RDC of the plurality of RDCs as one of observable at the observation point or not observable at the observation point based on a reset order applied to the sequence of flip-flops; and outputting a list of the plurality of RDCs classified as observable at the observation point.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: February 20, 2024
    Assignee: Synopsys, Inc.
    Inventors: Fahim Rahim, Paras Mal Jain, Rajarshi Mukherjee, Deep Shah, Satrajit Pal, Dipit Ranjan Senapati, Abhishek Kumar
  • Patent number: 11907630
    Abstract: A method is provided for performing power validation on an integrated circuit (IC) design based on a power assertion specification. The method includes receiving the power assertion specification for the IC design, where the power assertion specification includes a predicted power consumption. Power consumption of the IC design is estimated according to power assertions specified in the power assertion specification. The estimated power consumption is compared against the predicted power consumption included in the power assertion specification. The IC design is determined to be associated with a power assertion failure based on results of the comparing. In response to determining that the IC design is associated with the power assertion failure, the IC design is refined to remedy the power assertion failure.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: February 20, 2024
    Assignee: Synopsys, Inc.
    Inventors: Jitendra Kumar Gupta, Alexander John Wakefield
  • Patent number: 11899586
    Abstract: A memory address may be received at an m-way set-associative cache, which may store a set of cache entries. The memory address may be partitioned into a tag, an index, and an offset. The m-way set-associative cache may include a first structure to store a first subset of tag bits corresponding to the set of cache entries and a second structure to store a second subset of tag bits corresponding to the set of cache entries. The index may be used to select a first set of entries from the first structure. A first portion of tag bits of the memory address may be matched with the first set of entries. A cache status may be determined based on matching the first portion of tag bits of the memory address with the first set of entries.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: February 13, 2024
    Assignee: Synopsys, Inc.
    Inventor: Karthik Thucanakkenpalayam Sundararajan
  • Patent number: 11900042
    Abstract: In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: February 13, 2024
    Assignee: Synopsys, Inc.
    Inventors: Kevin Dean Lucas, Yudhishthir Prasad Kandel, Ulrich Welling, Ulrich Karl Klostermann, Zachary Adam Levinson
  • Patent number: 11893332
    Abstract: For each circuit element in a pair of launch and capture paths, a parameter value of the circuit element may be modified by a variation amount that is assigned to a class of circuit elements to which the circuit element belongs. Next, a timing slack may be computed for the pair of launch and capture paths.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: February 6, 2024
    Assignee: Synopsys, Inc.
    Inventors: Wenwen Chai, Li Ding
  • Patent number: 11894049
    Abstract: A memory cell comprises a pair of cross-coupled inverters as a storage element, a first inverter in the pair of cross-coupled inverters having a first output at a first node, a second inverter in the pair of cross-coupled inverters having a second output at a second node. A first complementary transmission gate includes a first nMOS pass gate and a first pMOS pass gate, connected between the first node and a first bit line. A second complementary transmission gate includes a second nMOS pass gate and a second pMOS pass gate, connected between the second node and a second bit line. A first word line is connected to gate conductors of the first and second nMOS pass gates in the first and second complementary transmission gates. A second word line is connected to gate conductors of the first and second pMOS pass gates in the first and second transmission gates.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: February 6, 2024
    Assignee: Synopsys, Inc.
    Inventors: Plamen Asenov, Victor Moroz
  • Patent number: 11874597
    Abstract: A method of improving mask data used in fabrication of a semiconductor device includes, in part, setting a threshold value associated with a defect based on stochastic failure rate of the defect, performing a first optimal proximity correction (OPC) of the mask data using nominal values of mask pattern contours, identifying locations within the first OPC mask data where stochastically determined mask pattern contours may lead to the defect, placing check figures on the identified locations to enable measurement of distances between the stochastically determined mask pattern contours, and performing a second OPC of the first OPC mask data so as to cause the measured distances to be greater than the threshold value.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: January 16, 2024
    Assignee: Synopsys, Inc.
    Inventors: Zachary Levinson, Yunqiang Zhang
  • Patent number: 11876516
    Abstract: A level shifter circuit includes a first current mirror coupled between a power terminal and a ground terminal, a second current mirror coupled between the power terminal and the ground terminal, and a level shifter. The level shifter includes a first transistor coupled to the first current mirror and a second transistor coupled to the second current mirror. The first current mirror and the second current mirror control a state of the first transistor and the second transistor.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: January 16, 2024
    Assignee: Synopsys, Inc.
    Inventors: Peter Kwang Lee, Kapil Dev Dwivedi, John Edward Barth
  • Patent number: 11868696
    Abstract: A method for designing a circuit includes adding, to a circuit design, a power switch configured to produce only one output over an acknowledgement port. The power switch does not include input and output supply ports. The method also includes adding, to the circuit design, an isolation circuit in which only one select pin is used to produce an output. The isolation circuit does not include isolation power and retention circuitry. The method also includes adding, to the circuit design, a retention circuit. The retention circuit includes a clock gating enabled register, a first AND gate connected to a clear pin of the register, and a second AND gate connected to a chip enable pin of the register. The method further includes compiling, by a processing device, the circuit design.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: January 9, 2024
    Assignee: Synopsys, Inc.
    Inventors: Swarup Kumar Pattanayak, Prathamesh Chandrashekhar Joshi
  • Patent number: 11868694
    Abstract: A system is disclosed that includes a memory, and a processor configured to perform operations stored in the memory. The processor performs the operations to analyze each of a first set of sequential elements of a plurality of sequential elements to determine an edge of a clock signal pattern of a clock associated with each of the first set of sequential elements causing an output change at corresponding one or more sequential elements of the first set of sequential elements. The processor further performs the operations to discard one or more cycles of the clock signal pattern of the clock from emulation that do not include the edge of the clock signal pattern that causes at least one sequential element of the first set of sequential elements to change the output and emulate remaining cycles of the clock signal pattern of the clock.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: January 9, 2024
    Assignee: SYNOPSYS, INC.
    Inventors: Bojan Mihajlovic, Alexander Rabinovitch, Fei Chen
  • Patent number: 11860227
    Abstract: A delay estimation system estimates a delay of a DUT for an emulation system. The delay estimation system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. The system applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and provides the timing graph to a compiler to perform placement and routing of the DUT.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: January 2, 2024
    Assignee: Synopsys, Inc.
    Inventors: Yanhua Yi, Yu Yang, Jiajun Fan, Vinod Kumar Nakkala, Vijay Sundaresan, Jianfeng Huang