Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, the image sensor comprises a boundary deep trench isolation (BDTI) structure disposed at boundary regions of a pixel region surrounding a photodiode. The BDTI structure has a ring shape from a top view and two columns surrounding the photodiode with the first depth from a cross-sectional view. A multiple deep trench isolation (MDTI) structure is disposed at inner regions of the pixel region overlying the photodiode, the MDTI structure extending from the back-side of the substrate to a second depth within the substrate smaller than the first depth. The MDTI structure has three columns with the second depth between the two columns of the BDTI structure from the cross-sectional view. The MDTI structure is a continuous integral unit having a ring shape.

Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, a stressor layer is formed in the source/drain space, a metal gate structure including part of the second semiconductor layer as channel regions is formed by a gate replacement process, after the metal gate structure is formed, the stressor layer is at least partially removed, and a source/drain contact comprising metal or a metallic material is formed in the source/drain space from which the stressor layer is at least partially removed.

Abstract: A computing circuit is provided. The computing circuit is disposed in a memory device and electrically coupled to a memory cell of the memory device. The computing circuit includes a weight decoder, a multiplier, an adder tree, and an accumulator. The weight decoder is configured to obtain a compressed weight from the memory cell and generate a decoded weight based on the compressed weight. The multiplier is configured to generate a partial-product by multiplying an input signal with the decoded weight. The adder tree is configured to generate a partial-sum by performing an addition operation based on the partial-product. The accumulator is configured to generate an accumulated sum by performing an accumulation operation based on the partial-sum and output an output signal based on the accumulated sum. The accumulated sum is left shifted based on a shift signal.

Abstract: An apparatus for automated wafer carrier handling includes a base plate and an active expansion component movably coupled to the base plate. The active expansion component is configured to change from a contracted form to an expanded form so as to be engaged with a top flange mounted on a wafer carrier.

Abstract: Provided are a package structure having stacked semiconductor dies with wavy sidewalls and a method of forming the same. The package structure includes: a first die and a second die bonded together; a first encapsulant laterally encapsulating the first die; and a second encapsulant laterally encapsulating the second die, wherein a second interface of the second die in contact with the second encapsulant is a wavy interface in a cross-sectional plane.

Abstract: A semiconductor structure includes a plurality of first logic cells having a first cell height, a plurality of second logic cells having a second cell height different than the first cell height, a plurality of third logic cells having the first cell height, and a plurality of metal lines parallel to each other in a metal layer. Each of the first logic cells includes a plurality of multiple-fin transistors. Each of the second logic cells includes a plurality of single-fin transistors. Each of the third logic cells includes a plurality of single-fin transistors. The first logic cells and the third logic cells are arranged in odd rows of a cell array, and the second logic cells are arranged in even rows of the cell array. The metal lines inside the first and third logic cells are wider than the metal lines inside the second logic cells.

Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.

Abstract: A method for manufacturing a semiconductor device includes forming a first fin structure and a second fin structure, wherein an isolation region is located between the fin structures, and wherein a space is located between the fin structures and above the isolation region; depositing a blocking layer over the first fin structure, the isolation region, and the second fin structure, wherein an upper portion of the blocking layer is located above the first fin structure and the second fin structure, and wherein a lower portion of the blocking layer fills the space located between the first fin structure and the second fin structure; removing the upper portion of the blocking layer; and while the lower portion of the blocking layer remains over the isolation region, performing an etch process to recess the first fin structure and the second fin structure.

Abstract: A communication system and an operation method thereof are provided. A transmitting device transmits a data unit to a receiving device through a data channel of a communication interface. The transmitting device calculates an original verification information unit of the data unit and synchronously transmits the original verification information unit to the receiving device through a verification information channel of the communication interface based on a transmission timing of the data unit in the data channel. After receiving a current data unit and before receiving a next data unit, the receiving device verifies whether the current data unit received from the data channel has errors in real time based on a current original verification information unit corresponding to the current data unit.

Abstract: A memory device includes a memory array, a multiply-accumulate (MAC) circuit and an encoder-decoder circuit. The MAC circuit performs a MAC operation on an encoded weight data stored in the memory array and an input data to generate a partial MAC result. An encoder of the encoder-decoder circuit is configured to encode m weight bits among n weight bits of weight data according to an encryption key to generate the encoded weight data, wherein m and n are positive integers, and m is less than n. A decoder of the encoder-decoder circuit is configured to detect an error in the partial MAC result according to the encryption key to generate a decoded partial MAC result.

Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first alignment pattern having a plurality of first scale patterns arranged in a first direction. The second semiconductor device is mounted over the first semiconductor device and includes a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns.

Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first alignment pattern having a plurality of first scale patterns arranged in a first direction. The second semiconductor device is mounted over the first semiconductor device and includes a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a chip structure including a substrate and a wiring structure over a first surface of the substrate. The semiconductor device structure includes a first seed layer over the wiring structure, a first inner wall of the first enlarged portion, and a second inner wall of the neck portion. The semiconductor device structure includes a second seed layer over a second surface of the substrate, a third inner wall of the second enlarged portion, and the first seed layer over the second inner wall of the neck portion. The second seed layer is in direct contact with the first seed layer.

Abstract: A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.

Abstract: A method for manufacturing a semiconductor device includes: forming a first waveguide structure and a second waveguide structure on a substrate in which the first waveguide structure and the second waveguide structure is spaced apart from each other by a recess; conformally forming an un-doped dielectric layer to cover the first and second waveguide structures and to form a gap between two corresponding portions of the un-doped dielectric layer laterally covering the first waveguide structure and the second waveguide structure, respectively; and forming a doped filling layer to fill the gap.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a buffer layer between the channel layer and the substrate. The method can further include forming a recess structure in the channel layer. The recess structure can include a bottom surface over the buffer layer. The method can further include forming a first epitaxial layer over the bottom surface of the recess structure. The first epitaxial layer can include a first atomic concentration of germanium. The method can further include forming a second epitaxial layer over the first epitaxial layer. The second epitaxial layer can include a second atomic concentration of germanium greater than the first atomic concentration of germanium.

Abstract: A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.

Abstract: Disclosed embodiments herein relate to an integrated circuit including power switches with active regions connected to form a contiguous region. In one aspect, the integrated circuit includes a first layer including a first metal rail extending in a first direction. In one aspect, the integrated circuit includes a second layer above the first layer along a second direction perpendicular to the first direction. The second layer may include active regions for power switches. In one aspect, the active regions of the power switches are connected to form a contiguous region extending in the first direction. The first metal rail may be electrically coupled to the active regions through via contacts. In one aspect, the integrated circuit includes a third layer above the second layer along the second direction. The third layer may include a second metal rail electrically coupled to some of the power switches through additional via contacts.