Patents Assigned to Taiwan Semiconductor Manufacturing Company, Ltd.
  • Semiconductor structure with source/drain multi-layer structure and method for forming the same
    Patent number: 11990550
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a S/D silicide layer formed on the S/D epitaxial layer, and the S/D silicide layer has a first width, the S/D epitaxial layer has a second width, and the first width is smaller than the second width. The semiconductor structure includes a dielectric spacer between the gate structure and the S/D silicide layer, and a top surface of the dielectric spacer is lower than a top surface of the gate structure.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • Semiconductor device and forming method thereof
    Patent number: 11990524
    Abstract: A method includes forming a dummy gate structure across a fin, in which the dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode, forming gate spacers on sidewalls of the dummy gate structure, forming source/drain epitaxial structures on sides of the dummy gate structure, performing a first etch process to the dummy gate electrode such that a recessed dummy gate electrode remains over the fin, performing a second etch process to the gate spacers such that recessed gate spacers remain over the sidewalls of the dummy gate structure, removing the recessed dummy gate electrode and the dummy gate dielectric layer after the second etch process to form a recess between the recessed gate spacers, forming a gate structure overfilling the recess, and performing a third etch process to the gate structure such that a recessed gate structure remains between the recessed gate spacers.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Chien Lin, Hsi Chung Chen, Cheng-Hung Tsai, Chih-Hsuan Lin
  • Vertical tunneling field-effect transistor cell
    Patent number: 11990531
    Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hay-Lay Chuang, Cheng-Cheng Kuo, Ming Zhu
  • Isolation structure for isolating epitaxially grown source/drain regions and method of fabrication thereof
    Patent number: 11990525
    Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang, Jhon Jhy Liaw
  • Semiconductor device having fully oxidized gate oxide layer and method for making the same
    Patent number: 11990545
    Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsu-Hsiu Perng, Yun-Chi Wu, Chia-Chen Chang, Cheng-Bo Shu, Jyun-Guan Jhou, Pei-Lun Wang
  • Magnetic tunnel junction device and method of forming same
    Patent number: 11990167
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Jhih Shen, Kuang-I Liu, Joung-Wei Liou, Jinn-Kwei Liang, Yi-Wei Chiu, Chin-Hsing Lin, Li-Te Hsu, Han-Ting Tsai, Cheng-Yi Wu, Shih-Ho Lin
  • Capping layer overlying dielectric structure to increase reliability
    Patent number: 11990400
    Abstract: Some embodiments relate to a method for forming an integrated chip, the method includes forming a first conductive wire and a second conductive wire over a substrate. A dielectric structure is formed laterally between the first conductive wire and the second conductive wire. The dielectric structure comprises a first dielectric liner, a dielectric layer disposed between opposing sidewalls of the first dielectric liner, and a void between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is formed along an upper surface of the dielectric structure. Sidewalls of the dielectric capping layer are aligned with sidewalls of the dielectric structure.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Ya Lo, Chi-Lin Teng, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Shao-Kuan Lee, Cheng-Chin Lee
  • Memory device
    Patent number: 11990180
    Abstract: A memory device is provided. The memory device includes a cell array having a plurality of cells, each of the plurality of cells operative to store a bit value. The memory device further includes a reset circuit connected to the cell array. The reset circuit is operative to reset, in parallel, the bit value stored in each of the plurality of cells to a predetermined bit value.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shih-Lien Linus Lu
  • Method of cleaning, support, and cleaning apparatus
    Patent number: 11986869
    Abstract: A method of cleaning includes placing a semiconductor device manufacturing tool component made of quartz on a support. A cleaning fluid inlet line is attached to a first open-ended tubular quartz projection extending from an outer main surface of the semiconductor device manufacturing tool component. A cleaning fluid is applied to the semiconductor device manufacturing tool component by introducing the cleaning fluid through the cleaning fluid inlet line and the tubular quartz projection.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Chen Ho, Chih Ping Liao, Ker-hsun Liao, Chi-Hsun Lin
  • Shift register having low power mode
    Patent number: 11990194
    Abstract: The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang
  • Integrated circuit packages having support rings
    Patent number: 11990381
    Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
  • Operation methods for ovonic threshold selector, memory device and memory array
    Patent number: 11990182
    Abstract: An operation method for a memory device is provided. The memory device includes a two-terminal selector and a resistance variable storage element coupled to the two-terminal selector. The method includes providing a voltage pulse to the memory device. A voltage applied across the two-terminal selector during a falling part of the voltage pulse falls below a holding voltage of the two-terminal selector. A voltage falling rate of the falling part at which the voltage applied across the two-terminal selector reaches the holding voltage is raised for reducing threshold voltage drift of the two-terminal selector.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hengyuan Lee, Cheng-Hsien Wu, Yu-Sheng Chen, Elia Ambrosi, Chien-Min Lee, Xinyu Bao
  • Transistorless memory cell
    Patent number: 11990169
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes an operative memory device coupled to a bit-line. The operative memory device is configured to store a data state. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus includes one or more regulating MTJ devices that are configured to control a current provided to the operative memory device. The one or more regulating MTJ devices respectively include a free layer, a dielectric barrier layer on the free layer, and a pinned layer separated from the free layer by the dielectric barrier layer. The pinned layer covers a center of a surface of the dielectric barrier layer that faces the pinned layer.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Katherine Chiang, Chung Te Lin, Min Cao, Yuh-Jier Mii, Sheng-Chih Lai
  • Memory system with physical unclonable function
    Patent number: 11990183
    Abstract: A method includes: programming a first bit of a physical unclonable function into a first memory cell; and generating, by a first memory circuit in the first memory cell, a first current indicating a logic value of the first bit. The programming the first bit includes: turning on a first switch in the first memory circuit and at least one second switch in at least one second memory circuit in the first memory cell in response to a first bit line signal, to program one of the first memory circuit and the at least one second memory circuit while rest of the first memory circuit and the at least one second memory circuit is not programmed, according to the first bit line signal. A memory device and a system are also disclosed herein.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Meng-Sheng Chang
  • Method for forming sidewall spacers and semiconductor devices fabricated thereof
    Patent number: 11990374
    Abstract: Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Shi Ning Ju, Yi-Ruei Jhan, Kuan-Lun Cheng, Chih-Hao Wang
  • Dummy die placement without backside chipping
    Patent number: 11990429
    Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Wei Wu, Ying-Ching Shih, Kung-Chen Yeh, Li-Chung Kuo, Pu Wang, Szu-Wei Lu
  • Bonding structures in semiconductor packaged device and method of forming same
    Patent number: 11990428
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao Chun Liu, Ching-Wen Hsiao, Kuo-Ching Hsu, Mirng-Ji Lii
  • Back-end-of-line passive device structure
    Patent number: 11990401
    Abstract: A device structure according to the present disclosure includes a passivation layer, a first conductor plate layer disposed on the passivation layer, a second conductor plate layer disposed over the first conductor layer, a third conductor plate layer disposed over the second conductor layer, and a fourth conductor plate layer disposed over the third conductor layer. The second conductor plate layer encloses the first conductor plate layer and the fourth conductor plate layer encloses the third conductor plate layer. The device structure, when used in a back-end-of-line passive device, reduces leakage and breakdown due to corner discharge effect.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Chieh Hsiao, Hsiang-Ku Shen, Yuan-Yang Hsiao, Chen-Chiu Huang, Dian-Hau Chen
  • Semiconductor device and method for making the same
    Patent number: 11990416
    Abstract: A semiconductor device includes a gate structure disposed in a first dielectric layer, a conductive segment disposed in the first dielectric layer and separated from the gate structure, a second dielectric layer disposed over the first dielectric layer, a first contact penetrating the second dielectric layer and electrically connected to the gate structure, a second contact penetrating the second dielectric layer and electrically connected to the conductive segment, and a silicon nitride-based layer surrounding at least one of the first and second contacts and connected between the second dielectric layer and the at least one of the first and second contacts. A method for making the semiconductor device is also provided.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsinhsiang Tseng, Chi-Ruei Yeh, Tsung-Yu Chiang
  • Package structure having at least one die with a plurality of taper-shaped die connectors
    Patent number: 11990383
    Abstract: A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang