Abstract: A FET with a buried gate structure. The FET's gate electrode comprises a plurality of buried gate structures, the tops of which extend above the substrate's top surface and the bottoms of which are buried to a depth at least equal to that of the bottom of the channel layer, or the 2DEG plane within a channel layer for a HEMT, such that the buried gate structures contact the channel layer only from its sides. A head portion above and not in contact with the substrate's top surface contacts the tops of and interconnects all of the buried gate structures. Drain current is controlled by channel width modulation by lateral gating of the channel layer by the buried gates structures. The FET may include at least one field plate which comprises a slit structure in which the field plate is divided into segments.

Abstract: A multicolor imaging device capable of imaging two or more wavelengths with a single pixel comprises an avalanche photodiode having a material composition such that only one carrier causes substantially all of the impact ionization that occurs within the photodiode. The photodiode is arranged such that, when reverse-biased, the photodiode's gain varies with the photon energy of incident light. The photodiode, preferably a PIN avalanche photodiode or a separate absorber-multiplier photodiode, produces an output signal which can include at least two components produced in response to two different wavelengths of incident light. Circuitry receiving the output signal would typically include a means of extracting each of the components from the output signal.

Abstract: A hybrid device package comprising a baseplate, a balanced composite structure (BCS) on the baseplate, a first IC on the BCS, and at least one additional IC physically coupled to the first IC. The coefficient of thermal expansion (CTE) for the stack formed from the BCS and the first IC is arranged to be approximately equal to that of the baseplate, thereby reducing the thermal stress to which the at least one additional IC is subjected when cooled to its operating temperature which might otherwise result in physical damage to the IC. The baseplate is preferably an alumina ceramic baseplate. In one embodiment, the first IC is a readout IC (ROIC), the at least one additional IC is a detector array IC which is on the ROIC, and the hybrid device package is a focal plane array (FPA).

Abstract: A coated granular filtration medium is formed by the deposition of an electrolyte layer onto core particles. The electrolyte layer comprises a cationic polyelectrolyte. The coated granular filtration medium provides a synergistic combination of filtration and in situ coagulation that enables efficient, effective, and economical decontamination of industrial and other wastewaters.

Abstract: A magnetic field coil assembly includes a plurality of stacked dielectric layers, each of the plurality of stacked dielectric layers having a partial-loop conductive trace on a first side of the layer, a via interconnect in communication with the partial-loop conductive trace and extending from the first side of the layer to a side of the layer opposite from the first side, and a vapor cell reception aperture; and a vapor cell axially extending through the plurality of vapor cell reception apertures so that the plurality of partial-loop conductive traces is electrically connected serially to form a continuous coil disposed around the vapor cell that would create a magnetic field upon application of a current.

Abstract: Methods, systems, and apparatus that filters noise within a signal collected by a detector assembly. The detector assembly includes a first semiconductor layer of a first type configured to receive a photon. The detector assembly includes a second semiconductor layer of a second type. The second semiconductor layer is formed above the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are configured to collect a signal. The detector assembly includes an interface layer including an insulator portion for filtering noise. The interface layer is formed on the second semiconductor layer. The detector assembly includes a metal contact layer formed on the interface layer. The interface layer is configured to capacitively couple the first semiconductor layer and second semiconductor layer with the metal contact layer.

Abstract: A method of fabricating a voltage-tunable liquid crystal-based notch filter requires filling at least two LC cells with cholesteric LC material to create LH and RH LC cells while applying heat to the cell substrates such that their temperatures are raised to near, but below, the clearing point, such that the LC material remains in the cholesteric state. An AC voltage is applied and turned off repeatedly while the LC cells cool down to room temperature, to cause the LC molecules to temporarily deviate from their intrinsic helical alignment. The cells are passed under a UV light sufficient to create cross-linked polymer networks, and self-compensation is used to compensate for in-band retardation. The resulting LH and RH LC cells are stacked such that the electrodes on adjacent substrates are connected to form a common electrode.

Abstract: A FET employing a micro-scale device array structure comprises a substrate on which an epitaxial active channel area has been grown, with a plurality of micro-cells uniformly distributed over the active channel area. Each micro-cell comprises a source electrode, a drain electrode, and at least one gate electrode, with a first metal layer interconnecting either the drain or the source electrodes, a second metal layer interconnecting the gate electrodes, and a third metal layer interconnecting the other of the drain or source electrodes. Each micro-cell preferably comprises a source or drain electrode at the center of the micro-cell, with the corresponding drain or source electrode surrounding the center electrode. The number and width of the gate electrodes in each micro-cell may be selected to achieve a desired power density and/or heat distribution, and/or to minimize the FET's junction temperature. The FET structure may be used to form, for example, HEMTs or MESFETs.

Abstract: A conformal coating that resists fouling by waterborne contamination in aquatic environments, a method for fabricating the coating, and a filter having such a coating are disclosed. The coating comprises a hydrophilic polymer and a surfactant wherein the surfactant undergoes a phase change upon exposure to a saline solution. Also disclosed are in situ methods for regenerating anti-fouling filters having the fouling resistant coating.

Abstract: A bidirectional amplifier includes first and second ports, with a first summing node connected to the first port and a second summing node connected to the second port. First and second gain stages are connected between the first and second summing nodes, respectively, and a first node. First and second feedback stages are also connected between the first and second summing nodes, respectively, and the first node. The amplifier operates in a first mode in which an amplified version of a signal applied to the first port is provided at the second port, or a second mode in which an amplified version of a signal applied to the second port is provided at the first port. The first and second gain stages are preferably first and second common emitter cascode arrangements, and the first and second feedback stages are preferably first and second emitter followers.

Abstract: A column-parallel dual-gain single-slope ADC comprises an input for receiving a signal Vin, a sample-and-hold stage which receives Vin and outputs sampled signal Vin,samp, a comparator, a counter, and a ramp generator which generates high-gain (HG) and low-gain (LG) ramps, with the ratio of the LG ramp slope to the HG ramp slope being greater than 1. During a coarse conversion phase, Vin,samp is compared with a threshold voltage Vthresh, and a flag is set to a first or second state depending on the comparison. During a fine conversion phase, if the flag is in the first state, the HG ramp is provided to the comparator and its output toggles when the ramp voltage becomes equal to Vin,samp. If the flag is in the second state, the LG ramp is provided to the comparator and its output toggles when the LG ramp voltage becomes equal to Vin,samp.

Abstract: A flat optogenetic cuff interface (FOCI) is configured for functional optical stimulation of axons in a single fascicle of a peripheral nerve bundle in which the axons have been genetically modified to express light sensitive proteins for excitation or inhibition of the nerves. The FOCI is configured to gradually reshape the single fascicle to a final height between 0.2 mm and 0.5 mm by reorganizing the individual axons within the fascicle without reshaping (and damaging) the individual axons. The FOCI facilitates stimulation of axons over the entire cross-section of the reshaped fascicle within the power limitations for pulsed laser energy. An electrical interface may be included to sense nerve activity of either the stimulated axons to provide closed-loop feedback to control the optical sources or stimulated axons of a different modality to record the response.

Abstract: An arrangement for making electrical contact to a vertical capacitor having top and bottom metal layers separated by a dielectric, and at least one trench. Recesses are formed in an oxide layer over the capacitor to provide access to the top and bottom metal layers. The recesses include contacting portions preferably positioned such that there is no overlap between them and any of the trenches. Metal in the recesses, preferably copper, forms electrical contacts to the vertical capacitor's metal layers and enables reliable bonding to copper metallization on other layers such as an ROIC layer. ‘Dummy’ capacitors may be tiled on portions of the IC where there are no vertical capacitors, preferably with the top surfaces of their top metal at a height approximately equal to that of the top surface of the vertical capacitor's top metal, thereby enabling the IC to be planarized with a uniform planarization thickness.

Abstract: A method of matching images A and B of the same scene taken at different locations in the scene is provided by matching correspondence points in the image by evaluating pixel characteristics from nearby regions using a constellation of image chips and utilizing joint information across multiple resolution levels in a probability framework. Since each image chip is small, each chip in one image potentially can be matched with a number of chips in the other image. The accumulation of evidence (probability) over all image chips within the constellation over multiple resolution levels reduces the ambiguity. The use of a constellation of image chips removes the requirement present in most visual point matching techniques to special feature points (e.g. corner points) as the correspondence points.

Abstract: A cooling system that includes a substrate having a metallic face, at least one microporous wick formation in thermal communication with the metallic face, and a liquid delivery head positioned in complementary opposition to the metallic face, the liquid delivery head having at least one nozzle for directing a liquid towards the metallic face.

Abstract: Systems, devices, and methods including a bullet; a retroreflector array adhered to a base of the bullet, the retroreflector array having prism facets with a periodicity between 0.2 mm-2.0 mm; and a cover disposed over the retroreflector array and hermetically sealed at the base of the bullet; where the cover is disposed over the retroreflector array in a first position prior to firing, and where the cover is released from the base of the bullet in a second position after firing.

Abstract: An infrared detector system is provided for detecting infrared radiation from an infrared radiation source or a scene. The system includes a first area that is semiconductor-based and biased to produce negative luminescence, the first area including at least one semiconductor-based detector. The detector system further includes at least one additional area being semiconductor-based and biased to produce negative luminescence. A low-emissivity specular retro-reflector shield is configured to reflect infrared radiation and covers the first area and the at least one additional area. The shield defines an aperture to allow the at least one semiconductor-based detector to receive incident rays of the infrared radiation from the infrared radiation source or the scene via a low-scatter, low-emission optical system such that the radiation incident from the infrared radiation source or scene substantially fills the solid angle defined by the aperture at any point in the first area.

Abstract: A penetrator device has an outer housing of non-conductive, insulating material having a through bore, at least one conductive pin formed in one or two parts extending through the housing and having a first end portion and a second end portion extending out of the respective first and second ends of the housing, a first cladding layer bonded over the first end portion of the pin to form a first bonded assembly, a second cladding layer bonded over the second end portion of the pin to form a second bonded assembly, and the material of the first and second cladding layer comprising a corrosion resistant conductive material different from the pin material.

Abstract: A method of modeling the temperature profile of an IC transistor junction employs an efficient thermal simulation algorithm to implement a design tool for IC design applications. The junction area of a transistor is divided into an odd number of sub-sections of equal size. Each sub-section is modeled as an equivalent circular heat source having an area equal to that of a sub-section. Temperature profiles are determined for each of the equivalent circular heat sources, which are superimposed to provide a total thermal profile for the junction. The method is preferably employed with rectangular-shaped junction areas, and performed with a software-controlled microprocessor. The method may be integrated with an electronic circuit simulation program such as SPICE. The results of the modeling may be used to iteratively modify the component layout on an IC to improve its temperature performance and/or its component density.

Abstract: A moving object command link system includes a transmitter which outputs a EM beam and a steering mechanism which directs the beam toward one or more objects, at least one of which is moving. The system may include a variable attenuator which modulates the average output power of the beam, and/or a divergence controller to maintain a desired beam size. The beam may be polarized, and the system may include a polarization modulator which changes the beam's polarization in accordance with a predetermined sequence and schedule. The system may include a 1×2 switch to selectively provide the beam to one of first and second outputs. A tiltable dichroic beam splitter may be used to couple beams received from first and second objects to track cameras having respective boresights that are offset with respect to each other.