Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silkcon layer is then formed over the gate insulator layer. An first dielectric layser is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and a second silicon layer is formed on the semiconductor substrate. The first dielectric layer is then removed and another doping step is performed to dope the first silicon layer and the second silicon layer. A series of process is then performed to form a metal silicide layer on the first silicon layer and the second silicon layer and also to diffuse and activate the doped dopants.

Abstract: A MOSFET includes a gate oxide formed on a substrate. A thin dielectric layer is formed on the side walls of the gate. A gate is formed on the gate oxide. A first metal silicide layer is formed on top of the gate to increase the conductivity of the gate. Spacers are formed on the substrate and are separated with the gate by a space. Air gaps are formed between the gate and the spacers. First doped ion regions are formed aligned to the air gaps in the substrate, under a portion of the dielectric layer. Second doped ion regions are formed under the spacers in the substrate, next to the first doped ion regions. Third doped ion regions are formed in the substrate next to the second doped ion regions. The third doped ion regions have relatively highly doped ions to the first doped ion regions. The second doped ion regions are formed with immediately highly doped ions between the first and the third doped ion regions.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer of the first silicon layer and of the anti-reflection layer. A portion of the gate insulator layer is removed to have undercut spaces under the first silicon layer. A dielectric layer is then formed on the semiconductor substrate, on the sidewalls of the gate region, and within the undercut spaces. A spacer structure containing first type dopants is then formed on the sidewalls of the gate region. Following the removal of the anti-reflection layer, a second silicon layer containing second type dopants is formed over the semiconductor substrate and the first silicon layer.

Abstract: The method of forming MOS transistors includes the following steps. First, isolation regions are formed in the semiconductor substrate to separate the semiconductor substrate into an ESD protective region and a functional region. A gate insulator layer is formed on the substrate and a polysilicon layer is formed on the gate insulator layer. The polysilicon layer is then patterned to form gate structures on the ESD protective region and the functional region. The semiconductor substrate is doped for forming a first doped region and an insulator layer is formed over the semiconductor substrate. A portion of the insulator layer and a portion of the gate insulator layer are removed to form spacer structures and an insulator block. The semiconductor substrate is doped for forming a second doped region. An insulator opening is defined within the insulator block. The semiconductor substrate is then doped for forming a third doped region.

Abstract: The present invention proposes a method for fabricating shallow trench regions for isolation. An oxide hard mask is utilized for the silicon etching. A silicon oxynitride film is created near the trench corners to prevent the gate wrap-around and corner parasitic leakage. Forming trench regions on a semiconductor substrate by using a thick pad oxide layer as an etching hard mask. A thermal oxide film is grown to recover the etching damages. An undoped LPCVD amorphous silicon film is then deposited on entire surface of the semiconductor substrate. A high temperature/pressure oxidation process follows to convert the undoped amorphous silicon film into thermal oxide. A thick CVD oxide layer is deposited on the semiconductor substrate. The oxide film outside the trench regions is removed by using a CMP process. Finally, the MOS devices are fabricated on the semiconductor substrate by standard processes, and thus complete the present invention.

Abstract: A method for forming a fork-shaped capacitor of a dynamic random access memory cell is disclosed. The method includes forming a first conductive layer (118) over a semiconductor substrate (110), wherein at least a portion of the first doped polysilicon layer communicates to the substrate. A first dielectric layer is formed on the first conductive layer and is then patterned to form an opening therein and expose a portion of the first conductive layer. A second conductive layer is formed on the sidewall of the first dielectric layer and the exposed portion of the first conductive layer. A second dielectric spacer is formed on the sidewall of the second conductive layer. The first conductive layer is etched using the second dielectric layer as a mask, and a third conductive spacer is formed on the sidewalls of the second dielectric spacer. The second dielectric layer are then removed.

Abstract: The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a pad oxide layer on a semiconductor substrate, an n-well region is defined by implanting a high energy dose phosphorous in the semiconductor substrate. When the photoresist layer used for defining the n-well is stripped, a high energy and low dose blanket boron is implanted under the n-well region in the semiconductor substrate. Next, both the silicon nitride layer and the pad oxide layer are removed. A high temperature steam oxidation process is then performed to remove the crystalline defects, and the in-situ high temperature long time anneal is done to form a deep twin-well. A thick pad oxide layer formed by the high temperature steam oxidation is then removed, and an active region is defined followed by a standard oxidation process to grow a thick field oxide region.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the anti-reflection layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended sourcedrain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and the anti-reflection layer is then removed. A second silicon layer is formed on the semiconductor substrate and the first silicon layer. Another doping step is performed to dope the substrate to form a source/drain junction in the substrate under a region uncovered by the gate region and the undoped spacer structure.

Abstract: A method of fabricating buried bit line flash EEROM with shallow trench floating gate for suppressing the short channel effect is disclosed. The method comprises following steps. Firstly, a pad oxide layer and a conductive impurity (such as phosphorus) doped polysilicon layer is successively formed on the silicon substrate. Then, an oxidation process is performed to oxidize the polysilicon layer and to drive in the conductive impurities. After coating a patterned mask on the resultant surface to define a plurality of buried bit line regions, a dry etch is used to etch away the unmask regions till the silicon substrate is slightly recessed to form shallow trenches. Subsequently, the photoresist is stripped, and a gate dielectric layer, such as gate nitride or oxynitride layer is formed on the resultant surface.

Abstract: The present invention includes forming nitrogen-doped amorphous silicon layer on the gate structure and on a pad oxide. Nitride spacers are formed on the side walls of the gate structure. Then, the nitride spacers and the cap nitride are both removed by wet etching. Next, an ion implantation is carried out to dope dopants into the gate and in the N well. Doped regions for the NMOS device are next formed in the P well by performing a further ion implantation. An oxidation is performed to convert the nitrogen-doped amorphous silicon layer to a nitrogen-doped oxide layer. An ultra-shallow source and drain junctions and the extended source and drain are obtained by using the amorphous silicon layer as a diffusion source. Next, nitrogen spacers on the side walls of the oxide are formed. The oxide on the top of the gate and uncovered by the spacers are removed during the etching to form spacers. Self-aligned silicide (SALICIDE) and polycide are respectively formed on the exposed substrate and gate.

Abstract: The trench isolation structure in the present invention is as follows. A lower-half trench is in the substrate. An upper-half trench in the substrate is located above the lower-half trench and the upper-half trench has a larger width than the lower-half trench. A first insulating layer is right above the lower-half trench and the upper-half trench. A second insulating layer is located over the first insulating layer. A semiconductor layer is within the lower-half trench over a portion of the second insulating layer. A third insulating layer is located on the second insulating layer and the semiconductor layer and is located within the upper-half trench. The planarized deep-shallow trench isolation in the present invention can be employed for isolating CMOS and bipolar devices. A higher packing density than conventional trench isolation is provided.

Abstract: The method of forming buried contacts on a semiconductor substrate is as follows. At first, a gate insulator layer is formed on the substrate. An undoped silicon layer is then formed on the substrate, and a dielectric layer is formed on the undoped silicon layer. Portions of the dielectric layer, of the undoped silicon layer, and of the gate insulator layer are removed to define a buried contact opening. A doping step is carried out to dope the substrate for forming a buried contact region. A doped silicon layer is formed over the substrate. Next, a portion of the doped silicon layer is then removed to leave a silicon connection and a doped silicon sidewall. The dielectric layer is removed and a thermal oxidization is performed to form a thermal oxide layer on the exposed silicon surfaces. A gate region is defined by removing portions of the thermal oxide layer and the undoped silicon layer. The substrate is doped for forming a lightly doped source/drain region.

Abstract: The present invention includes performing a blanket ion implantation to form lightly doped drain regions (LDD) adjacent to gate structures. A second ion implantation is performed with tilted angle to form p channel punchthrough stopping regions. A third ion implantation is used to implant ions into a NMOS device region. Oxide spacers are then formed on gate structures. Next, a forth ion implantation is then carried out to dope ions into the substrate to form source and drain regions in the NMOS region and a NMOS cell region, respectively. Next, a fifth ion implantation is used to dope dopant into a PMOS device region, thereby forming source and drain regions in the PMOS device region. Subsequently, a high temperature thermal anneal is performed to form shallow junction of the devices.

Abstract: A circuit for reducing the transmission delay of the SDRAM by using a cascade-amplifying scheme. The circuit principally encompasses a memory array core for storing data, a main amplifier for initially amplifying the data, an MO-pair receiving amplifier for recognizing and amplifying the data, and an output neighborhood for outputting the data when the data convey a log data path. When the required data output from the memory array core is amplified by the main amplifier, the differential level of the required data will appear at both the far end and the near end of the data path. Therefore, the transmitted data at the far end can be amplified again as long as the differential level is sufficient.

Abstract: The present invention proposes a method for forming vertically modulated wells in a semiconductor substrate. The method can include the steps as follows. At first, isolation regions are formed over the substrate. A pad layer is then formed over the substrate and a photoresist layer is formed over the pad layer. Then, p-well regions are defined by removing portions of the photoresist layer. Next, first p-wells are formed in the substrate under the p-well regions. After forming a masking layer over the p-well regions, the photoresist layer is removed. A first thermal process is then performed. Second p-wells are formed in the substrate at a level below the first p-wells. Next, n-wells are formed in the substrate under regions uncovered by the masking layer and above the second p-wells. The masking layer and the pad layer are then removed. Finally, a second thermal process is performed to finish the formation of vertically modulated wells.

Abstract: A buried contact structure on a semiconductor substrate in the present invention is as follows. A gate insulator is on a portion of the substrate and a gate electrode is located over the gate insulator. A gate sidewall structure is on the sidewall of the gate electrode. A lightly doped junction region in the substrate is under the gate sidewall structure. A doped junction region is in the substrate abutting the lightly doped junction region and is located aside from the gate insulator. A doped buried contact region is in the substrate next to the doped junction region. An interconnect is located over a first portion of the doped buried contact region.The buried contact structure can further include a shielding layer over a second portion of the doped buried contact region. For forming more connections, the buried contact structure can further have a dielectric layer over the interconnect, the substrate, the gate sidewall structure, and the gate electrode.

Abstract: A MOSFET with buried contacts and air-gap gate structure is disclosed. The MOSFET comprises trench isolation regions on a silicon substrate. A poly gate on the active region is formed of a gate dielectric layer and a polysilicon layer, wherein the polysilicon layer is in the midst of a portion of the gate dielectric layer so that there are two unoccupied gate dielectric regions at two sides of polysilicon layer. A first buried contact and second buried contacts are doped polysilicon layer being with respective vertical portions back to back adjacent two terminals of the gate dielectric layer and with respect horizontal portions extended to the trench isolation regions. A CVD oxide layer is formed atop the first buried contact, the poly gate, and the second buried contact to form the air gaps therein. The source/drain regions are underneath the first and second buried contacts, respectively.

Abstract: The present invention proposes a structure of nonvolatile memory cell with a textured tunnel oxide and a high capacitive-coupling ratio. A non-tunnel oxide is formed on the semiconductor substrate. The tunnel oxides with textured surfaces are formed on the semiconductor substrate and are separated by the non-tunnel oxide. The source and drain are formed aligned to the tunnel oxides in the semiconductor substrate. The floating gate, the interpoly dielectric and the control gate, are formed in turn over the tunnel and non-tunnel oxides. Due to the textured structure of the tunnel oxide, the high-density and high-speed nonvolatile memory can be achieved.

Abstract: A method for fabricating simultaneously a self-aligned silicided and an ESD protective transistor is disclosed. To improve operation speed, the MOS transistor is manufactured with an extended S/D junction; however, there is no salicide and LDD and, with a normal junction in the ESD protective transistor. The method comprises the steps of: thermally grown oxide layers on a defined source/drain region and a poly-Si surface of the gate structure, Then, a photoresist is masked on the functional device, and n-type ions are implanted to form a source/drain region in the ESD protection device. Then the photoresist is removed so as to form a nitride layer on all exposed surfaces of the substrate. An anisotropic etching back the nitride layer to form spacers on sidewalls of the gate structure in the functional device by using a photoresist on the ESD protective device is followed.

Abstract: The present invention discloses a structure for 3-D transistors with high electrostatic discharge (ESD) reliability. The 3-D transistors are fabricated on a substrate. The substrate has several recess portions and silicon islands. Several buried oxide regions are formed in the silicon islands and upper portions of the silicon islands are isolated from the substrate by the buried oxide regions. Then, a gate oxide layer is formed on the substrate. The upper portions of the silicon islands are enclosed by the gate oxide layer and the buried oxide region. A gate structure is defined on each of the recess portions and silicon islands. Two N-type source/drain regions are defined in each of the silicon islands adjacent to each of the gates on the silicon islands. Two P-type source/draid regions are fabricated in each of the recess portions adjacent to each of the gates on the recess portion. Spacers are defined on the sidewalls of the gates and abutting to the gates.