Abstract: Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

Abstract: A motor controller architecture and method of operating the same. The motor controller asynchronously generates multiphase control signals for a multi-phase electric motor, relative to the estimation of various state parameters used in generating those control signals. Latency between the state estimation task and the control signal generation task is addressed by storing a timestamp with each input data sample from the sensors, and maintaining that timestamp with the output data from state estimation. Knowledge of the timestamp value allows the control task to update the state estimates to compensate for the time difference between the input data sample and the current sampling period.

Abstract: Assessing open circuit and short circuit defect levels in circuits implemented in state of the art ICs is difficult when using conventional test circuits, which are designed to assess continuity and isolation performance of simple structures based on individual design rules. Including circuit blocks from ICs in test circuits provides a more accurate assessment of defect levels expected in ICs using the circuit blocks. Open circuit defect levels may be assessed using continuity chains formed by serially linking continuity paths in the circuit blocks. Short circuit defect levels may be assessed by using parallel isolation test structures formed by linking isolated conductive elements in parallel to buses. Forming isolation connections on a high metal level enables location of shorted elements using voltage contrast on partially deprocessed or partially fabricated test circuits.

Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: An apparatus includes multiple first channels configured to be coupled to a first boost capacitor and multiple second channels configured to be coupled to a second boost capacitor. Each channel includes a transistor switch and a gate driver configured to drive the transistor switch. The gate drivers in the first channels include switch sub-arrays configured to control which transistor switch in the first channels is driven using a voltage from the first boost capacitor. The gate drivers in the second channels include switch sub-arrays configured to control which transistor switch in the second channels is driven using a voltage from the second boost capacitor. The transistor switch in each channel may include first and second transistors having their sources coupled together, and each of the channels may further include a pull-down switch configured to pull the sources of the first and second transistors to ground.

Abstract: A mobile system for analyzing ECG data includes an analog front end module coupled to a mobile consumer device. The analog front end module is configured to collect ECG data from one or more leads and is operable to convert the analog ECG data to digital ECG data. The mobile consumer device is coupled to receive the digital ECG data, and is configured to perform QRS detection using a filter whose cutoff frequency is adapted to noise level in real time. The ECG signal is amplified non-linearly and three windowed threshold signals (D, E, J) are derived. The cutoff frequency for the QRS detection is dynamically selected as a function of the threshold signals. A sample in the amplified signal is identified to be a heart beat point only when the sample value is equal to the first threshold signal and greater than the filtered threshold signal.

Abstract: A memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines.

Abstract: Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.

Abstract: Systems and devices for smooth light load operation in a DC/DC converter are presented. The disclosed systems and methods enable smooth discontinuous conduction mode (DCM)/continuous conduction mode (CCM) transition. The disclosed systems and methods of smooth light load operation in a DC/DC converter may also avoid the generation of sub-harmonics during light load operation. In an example embodiment, a rising ramp is used to control the ON time of the converter oscillator, while a falling ramp controls the OFF time. During DCM operation, the minimum value of the falling ramp is clamped. The clamping of the falling ramp ensures a substantially similar level of the error amplifier output in both CCM and DCM and avoids disturbances caused by a difference in the error amplifier outputs between the modes.

Abstract: A processor system with an application and a maintenance function that would interfere with the application if concurrently executed. The processor system comprises a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output. The processor system also comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application.

Abstract: An electronic circuit includes a more-secure processor having hardware based security for storing data. A less-secure processor eventually utilizes the data. By a data transfer request-response arrangement between the more-secure processor and the less-secure processor, the more-secure processor confers greater security of the data on the less-secure processor. A manufacturing process makes a handheld device having a storage space, a less-secure processor for executing modem software and a more-secure processor having a protected application and a secure storage. A manufacturing process involves generating a per-device private key and public key pair, storing the private key in a secure storage where it can be accessed by the protected application, combining the public key with the modem software to produce a combined software, signing the combined software; and storing the signed combined software into the storage space.

Abstract: An electronic circuit includes a more-secure processor having hardware based security for storing data. A less-secure processor eventually utilizes the data. By a data transfer request-response arrangement between the more-secure processor and the less-secure processor, the more-secure processor confers greater security of the data on the less-secure processor. A manufacturing process makes a handheld device having a storage space, a less-secure processor for executing modem software and a more-secure processor having a protected application and a secure storage. A manufacturing process involves generating a per-device private key and public key pair, storing the private key in a secure storage where it can be accessed by the protected application, combining the public key with the modem software to produce a combined software, signing the combined software; and storing the signed combined software into the storage space.

Abstract: An electronic circuit includes a more-secure processor having hardware based security for storing data. A less-secure processor eventually utilizes the data. By a data transfer request-response arrangement between the more-secure processor and the less-secure processor, the more-secure processor confers greater security of the data on the less-secure processor. A manufacturing process makes a handheld device having a storage space, a less-secure processor for executing modem software and a more-secure processor having a protected application and a secure storage. A manufacturing process involves generating a per-device private key and public key pair, storing the private key in a secure storage where it can be accessed by the protected application, combining the public key with the modem software to produce a combined software, signing the combined software; and storing the signed combined software into the storage space.

Abstract: A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs. The system also comprises a register coupled to at least one of the processor cores for identifying active execution environments. The system also comprises a global interrupt handler operable to selectively route interrupts to one or more of the interrupt inputs of said plural processor cores. The system also comprises a conversion circuit having plural interrupt-related output lines, and said conversion circuit fed with at least some of said respective wait for interrupt outputs and respective security outputs and fed by said register.

Abstract: An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for interrupt output. The system further comprises a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs. The system further comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processors operable to configure said power control circuit in response to the interrupt signal.

Abstract: The objective of this invention is to provide a transfer mask that is able to accurately pass micro-balls onto terminal areas on a substrate. A thin plate transfer mask 200 is arranged facing a substrate 100, and possesses a plurality of through-holes 242 for the purpose of passing micro-balls (solder balls) onto a plurality of terminal areas 108 formed on one surface of a substrate 100. Slits 230, 232, 234, 236 formed in the surface of the transfer mask 200 extending in the length direction and the width direction of the transfer mask 200, inside the substrate edge P1 and outside the area in which the plurality of through-holes 242 is formed when it is facing the substrate 100.

Abstract: This invention is a method of operating a system having multiple finite state machines and a controller controlling an operational state of each finite state machine. Upon selection by the controller of a changed operational state, each finite state machine determines if it supports the changed operational state. If the finite state machine supports the changed operational state, it enters the changed operational state. If the finite state machine does not support the changed operational state, it enters an offline state. The controller may also determine whether a changed operational state is supported by each finite state machine.

Abstract: In a method and system for regulating an output voltage, a linear voltage regulator (LVR) includes an adjustable shunt regulator (ASR) having a limited gain, a feedback circuit (FC), and a compensation resistor (CR). The limited gain causes the output voltage of the ASR to change in response to a change in an input current of the ASR. The FC generates a feedback voltage reference in proportion to the output voltage, the feedback voltage reference being provided to the ASR to control the output voltage. The CR is coupled to the ASR and the FC. The input current flows through the CR to provide a compensating voltage across the CR. The compensating voltage is provided to the feedback circuit to compensate the limited gain, thereby providing the output voltage that is substantially independent of the input current.

Abstract: A method of forming a transistor comprising forming a gate structure over an n-type semiconductor body and forming recesses substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown in the recesses and a silicon cap layer is formed over the silicon germanium. Further introduction of impurities into the silicon germanium to increase the melting point thereof and implanting p-type source/drain regions in the semiconductor body is included in the method. The method concludes with performing a high temperature thermal treatment.

Abstract: In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.