Abstract: A closed loop amplifier adapted to be directly connected to a battery having a battery voltage for powering the amplifier. The amplifier includes an amplifier stage having a node for receiving a control voltage for controlling a common mode voltage of the stage, a digital voltage indicator for generating a digital value corresponding to the battery voltage, and a common mode voltage supply providing the control voltage corresponding to the digital value. In a preferred embodiment, a Class-D amplifier is powered by a power supply providing power by way of a power supply voltage node and a ground node, the amplifier having improved common-mode voltage control. A first integrator stage receives an input signal and provides an output signal, the integrator stage having a first common-mode reference voltage applied thereto for control of the common-mode voltage of the integrator stage.

Abstract: System and method for integrated circuit manufacturing. A preferred embodiment comprises transmitting a first set of data to integrated circuits (ICs) while they are in an on-wafer state and having each IC store the first set of data into memory, transmitting a second set of data to the ICs and having the ICs compare the second set of data with the first set of data stored in the memory, reading out the results of the comparisons, and marking an IC as being defective if the comparison indicates that that the first set of data did not match the second set of data. Each IC features an antenna formed in the scribe line region adjacent to the IC so that communications can take place while the IC remains on the wafer without the need to use electrical probes.

Abstract: An asynchronous sample rate converter interpolates and filters a digital audio input signal to produce a filtered, up-sampled first signal. A FIFO memory receives the first signal and stores samples thereof at locations determined by a write address and presents stored samples from locations determined by a read address. The presented samples are passed through an interpolation and resampling circuit to produce a continuous-time signal which is re-sampled to produce a signal that is up-sampled relative to a desired output. That signal then is filtered and down-sampled to produce the output signal. Sample rate estimating circuitry computes a difference signal representative of a time at which a data sample of the audio input signal is received and a time at which a corresponding audio output sample is required, and address generation circuitry generates the read and write addresses.

Abstract: A BARC or other sacrificial fill layer etch comprises a selective etch chemistry of Ar/O2/CO. The BARC etch may be used in a via-first dual damascene method. After via (116) pattern and etch, a BARC/sacrificial fill layer (120) is deposited to fill the via (116) and coat the IMD (110). The excess sacrificial fill layer (120) material over the IMD (110) is removed using the Ar/O2/CO etch. A trench resist pattern (125) is formed over the BARC layer (120). During the main trench etch, portions of sacrificial fill layer (120) remain in the via to protect the etch-stop (104) at the bottom of the via (116).

Abstract: A method of variable length coding classifies each received symbol into one of a plurality of classifications having a corresponding variable length code table selected based upon a probability distribution of received symbols within the classification. The variable length codeword output corresponds to the received symbol according to the variable length code table corresponding to the classification of that received symbol. The plurality of classifications and the corresponding variable length code tables may be predetermined and fixed. Alternatively, the variable length code table may be dynamically determined with data transmitted from encoder to decoder specifying the variable length code tables and their configurations. Universal variable length code (UVLC) is used to code the symbols. Universal variable length code can instantiate to different variable length code tables with different parameters.

Abstract: The tristateless bus interface communication scheme according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, a low power embedded system bus architecture is provided with a bus interface connected to one or more peripheral interface using logic processes to enable microcontroller-based products and other components and devices to achieve a low power data transmission between central processors and peripheral devices. In accordance with an exemplary embodiment, a low power embedded system bus architecture comprises logic devices, for example, an OR gate for passing through only data from a selected peripheral device. To facilitate the throughput of data, the non-selected peripheral devices may only provide logic zero to the OR gate. The logic device arrangement may comprise any combination of logic devices which performs the function of eliminating the need for tristate buffers.

Abstract: A transconductor circuit, including a differential transconductor amplifier circuit. The transconductor circuit includes an input pair of transistors adapted to receive a differential input voltage, as well as a pair of output terminals adapted to provide a differential output current. A second pair of transistors provides current to the input pair of transistors. A floating voltage circuit is adapted to generate a floating voltage corresponding to a common-mode voltage of the differential output nodes and to control the second pair of transistors in response to the floating voltage to stabilize the common-mode voltage of the differential transconductor amplifier circuit.

Abstract: A metric calculator is disclosed having an interleaved structure for increasing the time during which metrics can be calculated by circuit components. A first interleave samples voltage of the received signal during a first phase and a second interleave samples voltage of the received signal during an opposite phase. The interleaved architecture calculates and updates metrics and decisions based on these metrics at code rate, without requiring completion of all ACS computations in one code period.

Abstract: A self-aligned multiple crown storage cell structure 10 for use in a semiconductor memory device and method of formation that provide a storage capacitor with increased capacitance. A double crown storage cell structure embodiment 10 can be formed by patterning a contact via 18 into a planarized base layer that can include an insulating layer 12, an etch stop layer 14, and a hard mask layer 16, depositing a first conductive layer 20, etching the first conductive layer 20, etching the hard mask layer 16, depositing a second conductive layer 24 onto the conductive material-coated patterned via 18 and the etch stop layer 14, depositing a sacrificial (oxide) layer 26 onto the second conductive layer 24, etching the sacrificial layer 26, depositing a third conductive layer 28, and etching conductive material and the remaining sacrificial layer 26. The last several steps can be repeated to form a storage cell structure 10 with three or more crowns.

Abstract: A lead frame, method of making same and semiconductor package containing the lead frame. The semiconductor package includes the lead frame which includes an essentially flat, planar lead frame body and lead frame leads extending from the lead frame body, the lead frame leads extending partially out of the plane of the lead frame body. A semiconductor chip is disposed on the lead frame and an encapsulant encapsulates the lead frame body, the semiconductor chip and a portion of the lead frame leads, with a portion of the lead frame leads extending external to the encapsulant. The two dimensional cross section can be essentially in the shape of a "U", essentially sinusoidal in shape, the sinusoidal shape having an odd number of half cycles of the sinusoidal shape or essentially in the shape of a "W".

Abstract: In a dynamic random access memory unit 10, a circuit, 61.sub.0 -61.sub.N.sbsb.--.sub.1, 615, and 617, is provided in which a non-change of each address signal of an address signal group during a next consecutive clock cycle blocks the application of the read activation control signal to the memory unit 10. In this manner, the memory unit 10 is inactive (i.e., does not perform a read operation) during the modify portion of a read-modify-write operation so that potential conflicts in the operation of the memory unit 10 are avoided.

Abstract: An integrated automation development system (10) for controlling and coordinating manufacturing equipment (24) employs a plurality of server processes (14, 16, 22, 28, 34, 36). Each server process includes a messaging manager (45) for receiving ASCII messages, and an interpreter (43) for evaluating the received ASCII messages and identifying commands within the messages. The server process further includes a command manager (41) for receiving and executing the commands, and a logic controller (47) for managing the logic flow of the command execution by the command manager (41). The servers may include additional commands (48) that enable them to serve as queue servers (34), terminal servers (28), and other application-specific server processes.

Abstract: A semiconductor device (76) is provided with a high-voltage portion including NMOS transistor (78) and PMOS transistor (82b) and a low-voltage portion including NMOS transistor (80) and PMOS transistor 82(a). The high-voltage NMOS transistor (78) includes source/drain regions (90a, 90b) having N- regions (90a.sub.1, 90b.sub.1) that are self-aligned with a gate (78) and N+ regions (90a.sub.2, 90b.sub.2) that are self-aligned with sidewall spacers (91) formed on sidewalls of the gate (78) to improve reliability under continuous high voltage operating conditions. The low voltage NMOS transistor includes source/drain regions (92a, 92b) that are self-aligned with sidewall spacers (92) to permit channel lengths to be scaled to less than 2 microns.

Abstract: A method of dynamically interfacing an application processor with a plurality of peripheral ports is shown, including the use of an expanded memory interface for controlling a plurality of memory components for an application processor external to the interface. The application processor is connected to the expanded memory interface, which is in turn coupled to at least one status port to facilitate communication between the application processor and the status port.