Abstract: Disclosed is an integrated circuit memory comprising at least one column of memory cells parallel connected with one another and connected to at least one bit line, each memory cell being connected to a bit line by at least one access transistor, wherein said memory contains a protection transistor that is connected to the bit line and controlled so as to be made conductive so as to limit the voltage drop on the bit line, during the stages of the reading of the memory, when this drop in voltage goes beyond a threshold having a value smaller than a value that prompts the writing of an information element in a memory cell.

Abstract: A method for the manufacture of integrated circuits where it is desired to produce narrow conducting grids separated by a narrow gap and uses the lifting-up of silicon nitride (bird's bill) which is formed during a thick localized oxidation. A localized oxidation step is carried out and the oxide formed is totally removed. The edges (20, 22) of a nitride layer (14) stay overhanging. A conforming polycrystalline-silicon deposition enables silicon to be deposited uniformly, including beneath these edges. Finally, vertical anisotropic etching removes the silicon everywhere except beneath the overhanging edges, so that two silicon lines (28, 30) remain. An ion implantation (34) may be performed between the two lines. The method will find particular application for making anti-dazzle systems for photosensitive charge-coupled devices.

Abstract: A push-pull output stage for electronic integrated circuits includes two NPN transistors (Q1, Q2) connected in series between two supply terminals. The output (S) is the junction point of the transistors. A third NPN transistor (Q3) has its base and its collector connected respectively to the base and to the collector of Q1. Two current flow arms (R1, Q4 and R2, Q5) are formed, one to establish a current depending on the potential of the emitter of Q3 and the other to establish a current depending on the potential of the emitter of Q1. The arms are mounted in a current mirror arrangement, the second arm tending to copy the current of the first arm; the current mirror generating a current output (S2) representing a difference between the current set up in the second arm and the current copied from the first arm. This current output is used to control the conduction of the second transistor (Q2).

Abstract: Disclosed is a system with at least two complementary transistors, having n and p channels but comprising a heterostructure of junctions between III-V group materials. In order to balance the threshold voltages in the two channels, namely the n (2DEG) and p (2DHG) channels, at least two p and n delta doped layers are included in two layers of the heterostructure, at levels included between the channels (2DEG, 2DHG) and the gate electrodes. The n delta doped layer is then removed by localized etching right above the p channel transistor. Application to fast logic circuits.

Abstract: The disclosure relates to amplifiers using emitter follower type transistors and, more particularly, to means for the biasing of these emitter followers. The amplifier includes a follower transistor, a biasing circuit injecting a base biasing current into the base of the follower transistor, a current generator connecting the emitter of the follower transistor to a supply potential. According to one characteristic, the biasing circuit includes, firstly, a transistor called an image transistor, the emitter of which is connected to the emitter of the follower transistor and, secondly, a current injector for the injection, into the base of the follower transistor, of a current constituting a replica of the base current of the image transistor. One of the advantages of this arrangement is that it can be used to obtain the biasing circuit with transistors that are all of a same type, NPN or PNP, as the follower transistor.

Abstract: The disclosure relates to the making of the source and drain access regions of a field-effect transistor, these two regions being differentiated. The control region is defined by means of a three-layer mask of metal, resin and metal. A resin mask protects the drain access region, thus enabling the implantation of the source access region. After the dissolving of the resins, the drain access region is implanted.