Abstract: Receiving data at a first device transferred from a second device includes: storing a starting address with respect to a memory address space for a memory of the first device in a storage location within the first device. A request is received at the first device to transfer one or more data values from the second device, the request including a target address with respect to a communication channel address space for a communication channel between the first device and the second device. The second device determines whether the target address corresponds to a reserved address value designated as an indicator of a transfer to a memory address beyond the communication channel address space.

Abstract: Communicating among cores in a computing system comprising a plurality of cores, each core comprising a processor and a switch, includes: routing a packet from an origin core to a destination core over a route including multiple cores; and at each core in the route before the destination core, routing the packet to the next core in the route according to a respective symbol in a sequence of multiple symbols. The respective symbol has a first symbol value indicating a single likely direction and the respective symbol has a second symbol value indicating multiple less likely directions.

Abstract: A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.

Abstract: Performing atomic operations in a computing system includes: acquiring a lock by performing a primary atomic operation that is directly supported in circuitry of the computing system on a first memory address in a memory of the computing system; accessing a second memory address in the memory of the computing system after the lock has been acquired; completing a secondary atomic operation based on accessing the second memory address; and releasing the acquired lock after the secondary atomic operation has been completed.

Abstract: Managing cache memories in a computing system comprising multiple cores includes: assigning home cache locations for portions of data stored among caches in a group of caches of respective cores; accessing a first one of the portions of the cached data by sending an access request to a first home core of that first one of the portions of cached data; tracking a history of access for the first one of the portions of cached data; determining whether the tracked history of access for the first one of the portions of cached data exceeds or meets a predetermined condition, and re-assigning a home cache location of the first one of the portions of cached data from the first home core to a second, different home core when the predetermined condition is met or exceeded.

Abstract: Managing data in a computing system comprising multiple cores includes: assigning a first set of data to caches within cores of a first subset of fewer than all of the cores in the computing system, and assigning a second set of data to caches within cores of a second subset of at least some remaining cores in the computing system not already assigned; and maintaining cache coherence among caches of respective cores in the first subset in response to data stored in at least one of the cores in the first subset being modified, and maintaining cache coherence among caches of respective cores in the second subset in response to data stored in at least one of the cores in the second subset being modified.

Abstract: The present invention relates to a method, system, and computer program product for performing a computer program analysis. The computer program includes a plurality of instructions. The method performs a static analysis of the computer program to compute the states of a stack pointer (SP), a frame pointer (FP), and a link register (LR) at one or more instructions of the program. The static analysis is preferably performed at compile time. Further, the method computes the states of the SP, the FP, and the LR at the instructions as determined by a dynamic analysis, wherein the dynamic analysis is preferably modeled (performed) during the static analysis. Furthermore, the states determined by the static analysis and the dynamic analysis are compared. If a discrepancy is found between the two states, metadata (information operators) is inserted into the program.

Abstract: Managing data in a computing system comprising a plurality of cores includes assigning home cache locations of at least a first type of data associated with a first process executing on a first core to respective caches of one or more of the plurality of cores. Cores other than a home core, whose cache includes a home cache location for given cached data, access the given cached data by communicating with the home core. Home cache locations of at least a second type of data associated with the first process are assigned to a local cache of the first core. In response to migrating the first process to execute on a second core, home cache locations of the second type of data associated with the first process are re-assigned to a local cache of the second core.

Abstract: Managing processes in a computing system comprising one or more cores includes receiving a request for a first process on a first core to execute with at least one predetermined task of an operating system disabled on the first core. In response to the request, the operating system determines whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core. The operating system grants the request or rejects the request in response to determining whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises receiving subsets of instructions corresponding to different portions of a program, each subset assigned to one of the computation units; scheduling instructions in a given subset for execution on the assigned computation unit, including scheduling communication instructions that send to or receive from a different computation unit over the interconnection network; allocating registers in a given computation unit for storing values accessed by instructions in a subset assigned to the given computation unit; and scheduling instructions after allocating registers to account for spills of values stored in allocated register to memory, preserving the order of communication instructions scheduled before allocating registers.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises receiving an initial partitioning of instructions into initial subsets corresponding to different portions of a program; forming a refined partitioning of the instructions into refined subsets each including one or more of the initial subsets, including determining whether to combine a first subset and a second subset to form a third subset according to a comparison of a communication cost between the first subset and second subset and a load cost of the third subset that is based at least in part on a number of instructions issued per cycle by a computation unit; and assigning each refined subset of instructions to one of the computation units for execution on the assigned computation unit.

Abstract: A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.

Abstract: An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.

Abstract: Packets are processed in a system that comprises a plurality of interconnected processor cores. The system receives packets into one or more queues. The system associates at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate. The system maps a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and based on at least one rate associated with a node not in the set. The packets are processed in one or more processor cores including the mapped processor core according to the hierarchy.

Abstract: An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further comprises one or more interface modules including circuitry to transfer data to and from a device external to the tiles; and a sub-port routing network including circuitry to route data between a port of a switch and a plurality of sub-ports coupled to one or more interface modules.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises forming subsets of instructions corresponding to different portions of a program, the subsets of instructions being related according to a control flow graph; forming one or more memory analysis regions that include one or more of the subsets of instructions, where each subset of instructions is included in a single memory analysis region; analyzing each memory analysis region to partition memory objects and instructions that access the memory objects into equivalence classes such that instructions within an equivalence class only access objects in the same equivalence class; and assigning memory access instructions a given equivalence class to one of the computation units for execution on the assigned computation unit.

Abstract: A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions and is configurable to transmit data from an initial processor core or an input/output device to an intermediate processor core based on a first dimension ordering policy, and from the intermediate processor core to a destination processor core. The first dimension ordering policy specifies an ordering of the dimensions of the interconnection network when routing data through the interconnection network.

Abstract: An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, and coupling circuitry configured to couple data resulting from processing an instruction from at least one of the streams of instructions to the storage module and to the switch.

Abstract: The present invention provides a method and system for managing virtual addresses of a plurality of processes corresponding to an application. The method comprises designating a first set of ranges of virtual addresses to the plurality of processes, wherein the virtual addresses of the first set of ranges map to a memory region shared among the plurality of processes. Further, the method comprises designating a second set of ranges of virtual addresses to the plurality of processes, wherein the virtual addresses of the second set of ranges map to a memory region independently used by a process of the plurality of processes. Furthermore, the method comprises adding or removing virtual address ranges from one of the first set of ranges and the second set of ranges based on requirements of the application, wherein the addition or removal is performed in virtual addresses of the plurality of processes.