Patents Assigned to Tilera Corporation
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Patent number: 8112581Abstract: A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more directory controllers for respective portions of the main memory, each associated with corresponding storage for directory state. Each corresponding storage provides space for maintaining directory state for each memory line that is indicated as stored in at least one of the cache memories such that the space for maintaining directory state is independent of the size of the main memory.Type: GrantFiled: December 2, 2010Date of Patent: February 7, 2012Assignee: Tilera CorporationInventors: Anant Agarwal, Ian R. Bratt, Matthew Mattina
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Patent number: 8086554Abstract: Pattern matching in a plurality of interconnected processing engines includes: accepting a stream of input sequences over an interface and storing the input sequences; storing instructions for matching an input sequence to one or more patterns in memory accessible by a first set of one or more processing engines, and storing instructions for matching an input sequence to one or more patterns in memory accessible by a second set of one or more processing engines; distributing information identifying selected input sequences to the first and second sets of processing engines; and retrieving the identified input sequences to perform pattern matching in the first and second sets of processing engines.Type: GrantFiled: July 22, 2011Date of Patent: December 27, 2011Assignee: Tilera CorporationInventors: Kenneth M. Steele, Anant Agarwal
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Patent number: 8065259Abstract: Pattern matching in a plurality of interconnected processing engines includes: accepting a stream of input sequences over an interface and storing the input sequences; storing instructions for matching an input sequence to one or more patterns in memory accessible by a first set of one or more processing engines, and storing instructions for matching an input sequence to one or more patterns in memory accessible by a second set of one or more processing engines; distributing information identifying selected input sequences to the first and second sets of processing engines; and retrieving the identified input sequences to perform pattern matching in the first and second sets of processing engines.Type: GrantFiled: September 27, 2010Date of Patent: November 22, 2011Assignee: Tilera CorporationInventors: Kenneth M. Steele, Anant Agarwal
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Patent number: 8050256Abstract: A processor includes a plurality of processor tiles, each tile including a processor core, and an interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions in which an ordering of dimensions for routing data is configurable.Type: GrantFiled: July 8, 2008Date of Patent: November 1, 2011Assignee: Tilera CorporationInventors: Leiwei Bao, Ian Rudolf Bratt
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Patent number: 8045546Abstract: A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.Type: GrantFiled: July 8, 2008Date of Patent: October 25, 2011Assignee: Tilera CorporationInventors: Leiwei Bao, Ian Rudolf Bratt
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Patent number: 8018849Abstract: The flow of data in an integrated circuit is controlled. The integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a receive buffer to store data from the switch. At a first tile, a count is maintained of data that has been sent to a second tile without receiving an acknowledgement up to a credit limit. At the second tile, data that arrives from the first tile when the receive buffer is full is sent to a memory outside of the tile.Type: GrantFiled: December 21, 2005Date of Patent: September 13, 2011Assignee: Tilera CorporationInventor: David Wentzlaff
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Patent number: 7987321Abstract: A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.Type: GrantFiled: December 13, 2010Date of Patent: July 26, 2011Assignee: Tilera CorporationInventors: Anant Agarwal, Ian R. Bratt, Matthew Mattina
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Patent number: 7882307Abstract: An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.Type: GrantFiled: April 14, 2006Date of Patent: February 1, 2011Assignee: Tilera CorporationInventors: David Wentzlaff, Matthew Mattina, Anant Agarwal
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Patent number: 7877401Abstract: A method for processing data for pattern matching includes: receiving a first sequence of data values; and generating a second sequence of data values based on the first sequence and one or more patterns and history of data values in the first sequence, wherein the second sequence has fewer data values than the first sequence and all subsequences in the first sequence that match at least one of the one or more patterns are represented in the second sequence.Type: GrantFiled: May 24, 2007Date of Patent: January 25, 2011Assignee: Tilera CorporationInventors: Mathew Hostetter, Kenneth M. Steele, Vijay Aggarwal
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Patent number: 7853754Abstract: A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more directory controllers for respective portions of the main memory, each associated with corresponding storage for directory state. Each corresponding storage provides space for maintaining directory state for each memory line that is indicated as stored in at least one of the cache memories such that the space for maintaining directory state is independent of the size of the main memory.Type: GrantFiled: May 25, 2007Date of Patent: December 14, 2010Assignee: Tilera CorporationInventors: Anant Agarwal, Ian R. Bratt, Matthew Mattina
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Patent number: 7853774Abstract: An integrated circuit including a plurality of tiles. Each tile comprises a processor; a switch including switching circuitry to forward data words over data paths from other tiles to the processor and to switches of other tiles; and memory coupled to the switch to buffer data transmitted among the tiles. The switches form a plurality of networks among the tiles. At least one of the networks is configured to transmit data among the tiles using an approach that reserves sufficient buffer space in the memories coupled to the switches to avoid deadlock conditions, and at least one of the networks is configured to transmit data among the tiles using an approach to detect and recover from deadlock conditions.Type: GrantFiled: December 21, 2005Date of Patent: December 14, 2010Assignee: Tilera CorporationInventor: David Wentzlaff
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Patent number: 7853752Abstract: A multicore processor includes a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more input/output modules configured to couple data between an input/output interface and at least one of a memory interface and a cache memory. Each of at least some of the cache memories is assigned as a home location for caching a corresponding portion of the main memory, and is configured to maintain the cache memory based on whether a processor core or an input/output module is requesting access to the cache memory.Type: GrantFiled: May 25, 2007Date of Patent: December 14, 2010Assignee: Tilera CorporationInventors: Anant Agarwal, Matthew Mattina
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Patent number: 7853755Abstract: A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.Type: GrantFiled: May 25, 2007Date of Patent: December 14, 2010Assignee: Tilera CorporationInventors: Anant Agarwal, Ian R. Bratt, Matthew Mattina
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Patent number: 7814242Abstract: An integrated circuit includes a plurality of tiles. Each tile comprises a processor; a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles; a receive buffer to store the data received by the switch; and a sorting module to provide data to the processor from the receive buffer, the sorting module comprising one or more buffers that are each configured to store data from the receive buffer based on a tag in the data.Type: GrantFiled: December 21, 2005Date of Patent: October 12, 2010Assignee: Tilera CorporationInventor: David Wentzlaff
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Patent number: 7805577Abstract: An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further comprises one or more memory interface modules including circuitry to access an external memory, each memory interface module coupled to a switch of at least one tile. At least some of the tiles are configured to send a message to a memory interface module to determine whether previous memory transactions associated with a tile have been completed.Type: GrantFiled: April 14, 2006Date of Patent: September 28, 2010Assignee: Tilera CorporationInventors: Matthew Mattina, David Wentzlaff, Anant Agarwal
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Patent number: 7805392Abstract: Pattern matching in a plurality of interconnected processing engines includes: accepting a stream of input sequences over an interface and storing the input sequences; storing instructions for matching an input sequence to one or more patterns in memory accessible by a first set of one or more processing engines, and storing instructions for matching an input sequence to one or more patterns in memory accessible by a second set of one or more processing engines; distributing information identifying selected input sequences to the first and second sets of processing engines; and retrieving the identified input sequences to perform pattern matching in the first and second sets of processing engines.Type: GrantFiled: November 29, 2006Date of Patent: September 28, 2010Assignee: Tilera CorporationInventors: Kenneth M. Steele, Anant Agarwal
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Patent number: 7805575Abstract: A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; and a plurality of memory interfaces providing memory access paths from the cache memories to a main memory, at least some of the memory interfaces providing access paths to the main memory for multiple of the cache memories. Each of the memory interfaces is associated with a corresponding portion of the main memory, and includes a directory controller for the portion of the main memory.Type: GrantFiled: May 25, 2007Date of Patent: September 28, 2010Assignee: Tilera CorporationInventors: Anant Agarwal, Ian R. Bratt, Matthew Mattina
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Patent number: 7793074Abstract: An apparatus comprises a plurality of processor cores, and an interconnection network to route data among the processor cores based on destination information in the data. The processor cores are configured to forward the data to a final destination if the destination information indicates that a destination processor core has been reached, or to forward the data to other processor cores if the destination information indicates that a destination processor core has not been reached. The final destination is one of a plurality of destinations indicated by the destination information, the destinations including a plurality of portions of the destination processor core.Type: GrantFiled: April 14, 2006Date of Patent: September 7, 2010Assignee: Tilera CorporationInventors: David Wentzlaff, Anant Agarwal
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Patent number: 7774579Abstract: An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The tile is configured to control access to a resource of the tile based on access information associated with the resource.Type: GrantFiled: April 14, 2006Date of Patent: August 10, 2010Assignee: Tilera CorporationInventors: David Wentzlaff, Anant Agarwal
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Patent number: 7774553Abstract: A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; and a plurality of memory interfaces providing memory access paths from the cache memories to a main memory, at least some of the memory interfaces providing access paths to the main memory for multiple of the cache memories. Each of the memory interfaces is associated with a corresponding portion of the main memory, and includes a directory controller for the portion of the main memory.Type: GrantFiled: May 25, 2007Date of Patent: August 10, 2010Assignee: Tilera CorporationInventors: Anant Agarwal, Ian R. Bratt, Matthew Mattina