Patents Assigned to Vishay Intertechnology
  • Publication number: 20040041278
    Abstract: The present invention provides for a flip chip resistor having a substrate having opposite ends, a pair of electrodes formed from a first electrode layer disposed on the opposite ends of the substrate, a resistance layer electrically connecting the pair of electrodes, a protective layer overlaying the resistance layer, and a second electrode layer overlaying the first electrode layer and at least a portion of the protective layer. The present invention provides for higher reliability performance and enlarging the potential soldering area despite small chip size.
    Type: Application
    Filed: May 19, 2003
    Publication date: March 4, 2004
    Applicant: Vishay Intertechnology, Inc.
    Inventors: Leonid Akhtman, Sakaev Matvey
  • Patent number: 6680668
    Abstract: A fast heat rise resistor comprising a substrate, a foil bridge on the surface of the substrate, the foil bridge having an elevated portion and a contact portion, the elevated portion above the substrate, the contact portion in contact with the substrate, a conductive layer attached to the contact portion of said foil bridge. The activation energy and/or response time is reduced as the foil bridge is suspended over the substrate. Another aspect of the invention include a method of manufacturing the foil bridge and application to autoignition vehicle airbags.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: January 20, 2004
    Assignee: Vishay Intertechnology, Inc.
    Inventors: George V. Gerber, Anthony E. Troianello, Haim Goldberger
  • Patent number: 6671945
    Abstract: A fast heat rise resistor comprising a substrate, a foil bridge on the surface of the substrate, the foil bridge having an elevated portion and a contact portion, the elevated portion above the substrate, the contact portion in contact with the substrate, a conductive layer attached to the contact portion of said foil bridge. The activation energy and/or response time is reduced as the foil bridge is suspended over the substrate. Another aspect of the invention include a method of manufacturing the foil bridge and application to autoignition vehicle airbags.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: January 6, 2004
    Assignee: Vishay Intertechnology, Inc.
    Inventors: George V. Gerber, Anthony E. Troianello, Haim Goldberger
  • Patent number: 6669435
    Abstract: A system, method, and apparatus, for resistor tube feeding is disclosed. A tube magazine comprising a length of tubing and adapted for receiving precision resistor cores and compressed air is disclosed. The tube magazine may be connected to a laser spiraller and a terminal welder. The process of filling the tube magazine may be electronically controlled.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: December 30, 2003
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Thomas L. Bertsch, Daryl J. Klataske
  • Patent number: 6621142
    Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: September 16, 2003
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
  • Patent number: 6621143
    Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: September 16, 2003
    Assignee: Vishay Intertechnology, Inc
    Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
  • Patent number: 6562647
    Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate).
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: May 13, 2003
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6538300
    Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: March 25, 2003
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
  • Publication number: 20020185710
    Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate).
    Type: Application
    Filed: May 28, 2002
    Publication date: December 12, 2002
    Applicant: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6451074
    Abstract: A conductive polymer capacitor includes an anode formed from a porous metal body having an anode lead extending therefrom. A dielectric layer is formed by oxidizing a surface of the anode. A solid electrolyte is formed on the dielectric layer and includes first and second polymer layers. The second conductive polymer layer includes a polyaniline layer formed by dipping the metal body having the first conductive layer thereon into a solution of doped polyaniline dissolved in an organic solvent.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: September 17, 2002
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Alexander Bluvstein, Gerovich Vera, Alexander Osherov, Vitaly Strokhin
  • Patent number: 6441475
    Abstract: This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: August 27, 2002
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6324979
    Abstract: An device for use in an electro-pyrotechnic initiator comprises a header, a foil resistive strip, a substrate, and a current source. The substrate is mounted on the header. The foil resistive strip is mounted on the substrate. The energy source is connected to the resistive strip. When current flows through the resistive strip, the resistive strip generates enough heat to spark autoignition of a pyrotechnic material. The pyrotechnic material is in direct contact with the resistive strip. For an energy input of up to 115 microjoules, the resistive strip can cause autoignition in less than 25 microseconds. In a second embodiment, an electro-pyrotechnic initiator for use in a “smart” airbag system comprises a header, a foil resistive strip, a substrate, a current source connected to the resistive strip, and a control circuit. The control circuit is designed such that it will cause current to flow through the resistive strip when the circuit receives an appropriate signal.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: December 4, 2001
    Assignee: Vishay Intertechnology, Inc.
    Inventor: Anthony E. Troianello
  • Patent number: 6316287
    Abstract: A package for a semiconductor device is formed by a process which includes forming a metal layer in contact with a connection pad on the front side of a semiconductor die while the die is still a part of a wafer. The metal layer extends into the scribe line between the die and an adjacent die. A nonconductive cap is attached to the front side of the wafer, and the wafer is ground from its back side to reduce its thickness. A cut is made from the back side of the wafer, preferably by sawing and etching, to expose the metal layer. A nonconductive layer is formed on the back side of the wafer and a second metal layer is deposited over the nonconductive layer, the second metal layer extending into the scribe line where it makes contact with the first metal layer through an opening in the nonconductive layer. Preferably, a solder post is formed on the second metal layer to allow the finished package to be mounted on a printed circuit board.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: November 13, 2001
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6271060
    Abstract: This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: August 7, 2001
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 5206623
    Abstract: An electrical resistor which is fabricated from traces of resistive material on a substrate of insulating material. The traces are interconnected electrically in series by first links and in parallel by second alternating links, which are connected to different terminals on the substrate. The second links are cut, preferably by laser trimming, so as to select the value of resistance of the resistor by reducing the number of traces connected in parallel and increasing the number of traces connected in series. Where the resistance of each trace is "R", the value of the resistance is adjustable by severing the second links from R/n to nR, where n is the number of traces.
    Type: Grant
    Filed: May 2, 1991
    Date of Patent: April 27, 1993
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Michel Rochette, Paul R. Simon
  • Patent number: 4677413
    Abstract: A precision resistor exhibiting a temperature coefficient of resistance which is very low and which is virtually independent of time, and capable of accepting high power, comprises a resistive foil applied to a substrate by means of an appropriate cement, wherein the coefficient of thermal expansion of the substrate is either at zero or as close to zero as is possible, and wherein the resistivity versus temperature characteristic of the foil selected is adjusted so as to compensate for the thermal strain induced change in resistance which results when the temperature of the assembly changes, and the device is reacting to the application of power virtually without creating a transient phenomenon due to the flow of heat. Also a method for producing such a precision resistor.
    Type: Grant
    Filed: November 20, 1984
    Date of Patent: June 30, 1987
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Joseph Szwarc
  • Patent number: 4570150
    Abstract: A precision resistor of the type formed by defining a resistive path in a thin foil of resistance material attached to a substrate. Metallic interface layers are deposited on terminal pads between which the resistive path extends, so that when solder-coated copper leads are spot-welded to the terminal pads, the junction between the copper leads and the terminal pads is both a spot-weld and a solder connection.
    Type: Grant
    Filed: December 14, 1983
    Date of Patent: February 11, 1986
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Frank P. Sandone, Jr
  • Patent number: 4455744
    Abstract: A precision resistor using a resistance metal film etched into a long serpentine strip cemented to a substrate. This substrate is a composite of rigid materials and plastics. The composite thermal coefficient of expansion of the substrate is given a non-linearity which in turn induces a stress related non-linear resistance change in the cemented film when the temperature changes. This stress-induced non-linear change is of approximately the same shape as the inherent non-linearity of the resistance versus temperature of the metal film, but opposite in polarity, over a wide range of resistor operating temperatures. Over the range, a much closer approximation to complete temperature compensation is obtained than previously.
    Type: Grant
    Filed: March 1, 1982
    Date of Patent: June 26, 1984
    Assignee: Vishay Intertechnology, Inc.
    Inventor: Felix Zandman
  • Patent number: 4378549
    Abstract: Improved resistive electrical components are disclosed comprising an insulating or insulated substrate, a resistive foil bonded to the substrate having photoetched therein a pair of terminal pads for making electrical connections to the component and a system of resistive paths interconnecting the terminal pads, said system including an unadjustable section or sections and a plurality of adjustable sections, each having an adjustment tab associated therewith, said tab being removable to modify said section resistance and thereby altering the total resistance presented by the component between its terminal pads, the configurations of the sections differing from each other in a modified geometric progression so that the total resistance of said component is altered by a differing amount depending on which of the sections is modified by removal of its associated adjustment tab, whereby the total resistance of the component may be systematically varied in a sequence of successive steps to achieve a desired ultima
    Type: Grant
    Filed: September 10, 1980
    Date of Patent: March 29, 1983
    Assignee: Vishay Intertechnology, Inc.
    Inventor: Joseph Szware
  • Patent number: 4324547
    Abstract: Qualitative as well as quantitative evaluation of bite characteristics is performed by subjecting to bite forces pieces of material which exhibits photoelastic memory and studying the resulting impression with a polariscope. A permanent record can also be obtained.
    Type: Grant
    Filed: January 4, 1979
    Date of Patent: April 13, 1982
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Mircea Arcan, Benedict Heinrich