Patents Assigned to VLT, Inc.
  • Publication number: 20080112139
    Abstract: Power conversion apparatus can include a circuit board with power conversion circuitry and a package. The package may be formed by encapsulating areas of the circuit board assembly either before or after the interface contacts are attached to the circuit board. A method for encapsulating two sides of a substrate can include providing a mold that fills a larger first cavity to create a sealing force on a smaller second cavity. The encapsulant flows through the first cavity into the second cavity. A thermal extender can include a surface for mounting a heat dissipating power converter and a surface for mating with an external circuit board. Interface conductors may mate with contacts on the heat dissipating power converter and with conductive regions on the external circuit board. A heat sink may be thermally coupled to remove heat generated by the power converter.
    Type: Application
    Filed: January 15, 2008
    Publication date: May 15, 2008
    Applicant: VLT, INC.
    Inventors: Patrizio Vinciarelli, Michael LaFleur, Charles McCauley, Paul Starenas
  • Patent number: 7361844
    Abstract: Power conversion apparatus includes a circuit board with power conversion circuitry and a package having an upper portion and a lower portion that respectively enclose circuitry on a top surface and a bottom surface of the circuit board. The lower portion encloses a smaller region than that enclosed by the upper portion. The regions are arranged to define an overhang region on the bottom surface of the circuit board. Interface contacts are provided on the bottom surface in the overhang region for making electrical connections to the circuit board. A thermal extender includes a surface for mounting a heat dissipating power converter and a surface for mating with an external circuit board. Interface conductors mate with contacts on the power converter and with conductive regions on the external circuit board. A heat sink is thermally coupled to remove heat generated by the power converter.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: April 22, 2008
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Michael B. Lafleur, Charles I. McCauley, Paul V. Starenas
  • Patent number: 7353587
    Abstract: A method of manufacturing a magnetic core includes providing a substrate with magnetically permeable material that has a first region and a second region near the first region, providing support to maintain a juxtaposition between the first region and the second region, forming a slit through the magnetically permeable material between the first region and the second region, introducing a binding agent into the slit and removing the support; wherein the binding agent maintains the juxtaposition between the first region and the second region after the support is removed.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: April 8, 2008
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Eva M. Kenny-McDermott
  • Patent number: 7236086
    Abstract: A transformer having galvanically isolated windings defines a primary side and a secondary side of a power conversion apparatus. A switch couples power from a source on the primary side via the transformer to a load on the secondary side. A first circuit assembly has primary-side circuitry galvanically coupled to a port for connection to an input power source. The primary-side circuitry includes a primary-side communicator for sending or receiving control information used in controlling operation of the power conversion apparatus. A second circuit assembly has secondary-side circuitry galvanically coupled to a port for connection to a load. The secondary-side circuitry includes a secondary-side communicator for sending or receiving the control information.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: June 26, 2007
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Louis A. Bufano
  • Patent number: 7233469
    Abstract: Protection and filtering functions are provided for external circuits by internal circuits that use controlled elements.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: June 19, 2007
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Jay Prager
  • Patent number: 7212419
    Abstract: A method and apparatus for adaptively configuring an array of voltage transformation modules is disclosed. The aggregate voltage transformation ratio of the adaptive array is adjusted to digitally regulate the output voltage for a wide range of input voltages. An integrated adaptive array having a plurality of input cells, a plurality of output cells, or a plurality of both is also disclosed. The input and output cells may be adaptively configured to provide an adjustable transformer turns ratio for the adaptive array or in the case of an integrated VTM, an adjustable voltage transformation ratio for the integrated VTM. A controller is used to configure the cells and provide digital regulation of the output. A converter having input cells configured as a complementary pair, which are switched out of phase, reduces common mode current and noise. Series connected input cells are used for reducing primary switch voltage ratings in a converter and enabling increased operating frequency or efficiency.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: May 1, 2007
    Assignee: VLT, Inc.
    Inventor: Patrizio Vinciarelli
  • Patent number: 7202646
    Abstract: A droop compensation system includes a controlled current source that provides a scaled model of the PRM output current or VTM input current on an interface connection. A controlled resistance modeling the VTM effective series input resistance is connected across the interface terminal. The voltage developed across the controlled resistance by the controlled current establishes a correction signal representative of the VTM droop that is used to adjust the PRM output thereby compensating for the droop. A VTM control interface provides a mechanism for enabling and disabling the VTM. The VTM control circuitry may be powered by the interface connection, allowing the VTM to operate and process power when the VTM input voltage is below its normal minimum operating voltage, increasing the VTM dynamic range and allowing “soft start” into a capacitive load.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: April 10, 2007
    Assignee: VLT, Inc.
    Inventor: Patrizio Vinciarelli
  • Patent number: 7187263
    Abstract: A circuit board has apertures. Separate magnetic flux paths each form a closed loop that passes through at least one of the apertures and surrounds an interior space. The flux paths comprising portions that lie within magnetically permeable core pieces. At least two of the flux paths are oriented so that there is a straight line in the circuit board that passes through the interior spaces of the two flux paths without passing through any of the apertures that are included in the paths. An electrically conductive primary winding having a first segment that passes through the interior spaces of the permeable paths and a second segment located outside of the interior spaces. There are two or more electrically conductive secondary windings.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: March 6, 2007
    Assignee: VLT, Inc.
    Inventor: Patrizio Vinciarelli
  • Patent number: 7170764
    Abstract: A method and apparatus for adaptively configuring an array of voltage transformation modules is disclosed. The aggregate voltage transformation ratio of the adaptive array is adjusted to digitally regulate the output voltage for a wide range of input voltages. An integrated adaptive array having a plurality of input cells, a plurality of output cells, or a plurality of both is also disclosed. The input and output cells may be adaptively configured to provide an adjustable transformer turns ratio for the adaptive array or in the case of an integrated VTM, an adjustable voltage transformation ratio for the integrated VTM. A controller is used to configure the cells and provide digital regulation of the output. A converter having input cells configured as a complementary pair, which are switched out of phase, reduces common mode current and noise. Series connected input cells are used for reducing primary switch voltage ratings in a converter and enabling increased operating frequency or efficiency.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: January 30, 2007
    Assignee: VLT, Inc.
    Inventor: Patrizio Vinciarelli
  • Patent number: 7154250
    Abstract: Apparatus operates at a power level within a range of power levels that includes a rated maximum power level of the apparatus. The apparatus includes circuit elements to deliver power at an output voltage to a load from a source at an input voltage using an inductor selectively connected between the source and the load during a power conversion cycle. The inductor conducts a current having an average positive value during the power conversion cycle. A first switching device is interposed between the source and a first terminal of the inductor. A second switching device is interposed between a second terminal of the inductor and the load. A switch controller turns ON the first switching device during a time interval within the power conversion cycle during which the current is negative.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: December 26, 2006
    Assignee: VLT, Inc.
    Inventor: Patrizio Vinciarelli
  • Patent number: 7145786
    Abstract: In a preferred embodiment, a Sine Amplitude Converter (“SAC”) method and apparatus for VTMs converts a DC input voltage to a DC output voltage using a fixed transformation ratio at a frequency locked to a resonance. The SAC uses a resonant circuit including a transformer and complementary primary switches operating with balanced switching and a high power conversion duty cycle (e.g., above 94%) to perform high frequency, low noise, single stage power processing. The resonant circuit may have a low Q while enhancing conversion efficiency. Common-mode noise may be effectively reduced using symmetrical resonant power trains. In a preferred embodiment, a low profile (<0.16 inch high), low permeability “dog's bones” core structure, integrated with multi-layer PCB windings to complete SAC transformers, gives rise to a VTM manufacturing platform with greater than 400 Watts/cubic-inch power density and 95% efficiency, converting 100–150 Watts at the point of load.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: December 5, 2006
    Assignee: VLT, Inc.
    Inventor: Patrizio Vinciarelli
  • Patent number: 7038917
    Abstract: An interconnect architecture in which a substrate such as a printed circuit board includes multiple conductive layers separated by one or more interposed insulating layers, the conductive layers being adapted to receive a high density array of interconnect elements such as a ball grid array (BGA). In certain preferred embodiments, a printed circuit board may provide a very low resistance interconnect forming the drain and source terminals of a lateral power MOSFET device incorporating a high density array of alternating source and drain interconnect elements, such as a BGA. In such embodiments, source and drain currents may be routed on different conductive layers separated by one or more interposed insulating layers. The upper conductive layer may include laterally non-conductive regions accommodating conductive columns that are connected to the lower conductive layer.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: May 2, 2006
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Charles I. McCauley, Paul V. Starenas
  • Patent number: 7015561
    Abstract: A switching circuit has an active switch, a controller, and at least two terminals. The at least two terminals include two current control terminals for connection at two locations in another circuit. The controller is configured to turn the active switch off to block current between the two locations when the voltage between the two locations is of a first polarity and otherwise to turn the active switch on to conduct current between the two locations, whether or not the two current control terminals are the only ones of the at least two terminals that are connected to the other circuit.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: March 21, 2006
    Assignee: VLT, Inc.
    Inventors: John Saxelby, Jay Prager, Patrizio Vinciarelli, Estia Eichten
  • Patent number: 6984965
    Abstract: A Factorized Power Architecture (“FPA”) method and apparatus includes a front end power regulator (“PRM) which provides one or more controlled DC bus voltages which are distributed through the system and converted to the desired load voltages using one or more DC voltage transformation modules (“VTMs”) at the point of load. VTMs convert the DC bus voltage to the DC voltage required by the load using a fixed transformation ratio K=Vout/Vin and with a low output resistance. VTMs exhibit high power density, efficiency and, owing to their inherent simplicity and component utilization, reliability. VTMs may be paralleled and share power without dedicated protocol and control interfaces, supporting scalability and fault tolerance. Feedback may be provided from a feedback controller at the point of load to the front end or to upstream, on-board power regulator modules (“PRMs”) to achieve precise regulation.
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: January 10, 2006
    Assignee: VLT, Inc.
    Inventor: Patrizio Vinciarelli
  • Patent number: 6985341
    Abstract: Circuitry provides various protection mechanisms to an external circuit using actively controlled elements. The controlled elements may by controlled to provide overcurrent, overvoltage, or undervoltage protection to an external circuit.
    Type: Grant
    Filed: April 24, 2001
    Date of Patent: January 10, 2006
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Jay Prager
  • Patent number: 6975098
    Abstract: A Factorized Power Architecture (“FPA”) method and apparatus for supplying power to highly transient loads such as microprocessors includes a front end power regulator (“PRM) which provides a controlled DC bus voltage which is converted to the desired load voltage using a DC voltage transformation module (“VTM”) at the point of load. The VTM converts the DC bus voltage to the DC voltage required by the load using a fixed transformation ratio K=Vout/Vin where Vin>Vout and with a low output resistance. The response time of the VTM, TVTM is less than the response time of the PRM, TPRM. A first capacitance, C1, across the load is made large enough to support the microprocessor current requirement within a time scale, T1, which is preferably greater than or equal to the characteristic open-loop response time of the VTM by itself, TVTM.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: December 13, 2005
    Assignee: VLT, Inc.
    Inventor: Patrizio Vinciarelli
  • Patent number: 6969909
    Abstract: In accordance with one embodiment of the invention, a semiconductor device includes conductive pad areas, and each conductive pad area is electrically connected to a plurality of metal traces which are in turn each connected to diffusions. A conductive contact element such as a solder bump or via can be attached to each conductive pad area such that the contact elements are arranged in a repeating pattern having a first pitch. The semiconductor device can also include translation traces, and each translation trace can be electrically connected to two or more of the conductive contact elements. Each translation trace can have a interconnect element attached thereto. The interconnect elements can be arranged in a repeating pattern having a second pitch substantially greater than the first pitch.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: November 29, 2005
    Assignee: VLT, Inc.
    Inventor: Michael Briere
  • Patent number: 6940022
    Abstract: An electronic device includes a surface and a conductive termination on the surface. A protective conformal coating on the surface of the electronic device includes a window formed in the protective coating to expose a portion of the conductive termination. The exposed portion of the conductive termination is recessed in the conformal coating.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: September 6, 2005
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Jeffrey A. Curhan
  • Patent number: D510906
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: October 25, 2005
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Fred M. Finnemore, Michael B. Lafleur, Charles I. McCauley, Gary C. Keay, Scott W. Nowak, Basil Thompson
  • Patent number: D520947
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: May 16, 2006
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Fred M. Finnemore, Charles I. McCauley, Gary C. Keay, Scott W. Nowak, Basil Thompson