Patents Assigned to Xilinx, Inc.
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Patent number: 11848670Abstract: An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.Type: GrantFiled: April 15, 2022Date of Patent: December 19, 2023Assignee: Xilinx, Inc.Inventors: Juan J. Noguera Serra, Tim Tuan, Javier Cabezas Rodriguez, David Clarke, Peter McColgan, Zachary Blaise Dickman, Saurabh Mathur, Amarnath Kasibhatla, Francisco Barat Quesada
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Publication number: 20230401043Abstract: A computer-based visualization and refactoring system is capable of analyzing a computer program to determine computation tasks of the computer program and channels linking the computation tasks. The system generates, in a memory of computer hardware, a dataflow graph having nodes representing the computation tasks and edges representing the channels. The edges connect the nodes. Source code representations of the computation tasks are determined. Execution metrics of the computer program are determined. The nodes of the dataflow graph are annotated with the source code representations and the nodes and/or the edges are annotated with the execution metrics. The dataflow graph is displayed on a display device as annotated.Type: ApplicationFiled: June 9, 2022Publication date: December 14, 2023Applicant: Xilinx, Inc.Inventors: Maurits Maarten de Jong, Liam Fitzpatrick, Matthias Gehre, Maximilian Odendahl, Benoit Pradelle, Stefan Schuermans, Luis Gabriel Murillo Gómez
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Publication number: 20230401480Abstract: Hardware acceleration of machine learning (ML) designs includes translating an ML primitive into an intermediate representation. The intermediate representation is subdivided to specify a functional compute block. The functional compute block is sized according to a compute node primitive adapted for implementing the ML primitive on target hardware. An overlay is generated for the ML primitive, at least in part, by mapping the functional compute block to the compute node primitive. The overlay is synthesizable to implement the ML primitive on the target hardware. The overlay can be scheduled for operation within the target hardware as part of an ML design including the ML primitive.Type: ApplicationFiled: June 14, 2022Publication date: December 14, 2023Applicant: Xilinx, Inc.Inventors: Ehsan Ghasemi, Rajeev Patwari, Elliott Delaye, Jorn Tuyls, Ephrem C. Wu, Xiao Teng, Sanket Pandit
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Patent number: 11842168Abstract: An electronic system includes a mapping circuit configured to receive input samples of a dataset within a defined range of values. The mapping circuit is configured to perform comparisons that compare each input sample to each of a plurality of comparison values selected from the defined range of values. For each comparison, the mapping circuit generates an indication value specifying whether the input sample used in the comparison is greater than or equal to the comparison value used in the comparison. The system includes an adder circuit configured to generate a sum of the indication values for each comparison value and a memory configured to maintain counts corresponding to the comparison values. The counts are updated by the respective sums. The system includes a threshold detection circuit configured to determine, for the dataset, a threshold value or threshold range based on the counts read from the memory.Type: GrantFiled: September 25, 2021Date of Patent: December 12, 2023Assignee: Xilinx, Inc.Inventors: Sai Lalith Chaitanya Ambatipudi, Vamsi Krishna Nalluri, Sandeep Jayant Sathe, Chaithanya Dudha, Krishna Kishore Bhagavatula
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Patent number: 11836426Abstract: Detecting sequential access violations for high-level synthesis (HLS) includes performing a simulation, using computer hardware, of an application for HLS. During the simulation, accesses of the application to elements of an array of the application are detected. During the simulation, determinations of whether the accesses occur in a sequential order are made. An indication of whether the access occur in sequential order is generated.Type: GrantFiled: August 15, 2022Date of Patent: December 5, 2023Assignee: Xilinx, Inc.Inventors: Fangqing Du, Alexandre Isoard, Lin-Ya Yu, Hem C. Neema
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Publication number: 20230385040Abstract: A computer-based technique for processing an application includes determining that a loop of the application includes a reference to a data item of a vector data type. A trip count of the loop is determined to have an unknown trip count. The loop is split into a first loop and a second loop based on a splitting factor. The second loop is unrolled.Type: ApplicationFiled: May 24, 2022Publication date: November 30, 2023Applicant: Xilinx, Inc.Inventor: Ajit K. Agarwal
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Patent number: 11832035Abstract: Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.Type: GrantFiled: April 16, 2021Date of Patent: November 28, 2023Assignee: XILINX, INC.Inventors: Aman Gupta, Sagheer Ahmad, Ygal Arbel, Abbas Morshed, Eun Mi Kim
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Patent number: 11831743Abstract: Apparatus and associated methods relate to packet header field extraction as defined by a high level language and implemented in a minimum number of hardware streaming parsing stages to speculatively extract header fields from among multiple possible header sequences. In an illustrative example, the number of stages may be determined from the longest possible header sequence in any received packet. For each possible header sequence, one or more headers may be assigned to each stage, for example, based on a parse graph. Each pipelined stage may resolve a correct header sequence, for example, by sequentially extracting length and transition information from an adjacent prior stage to determine offset of the next header. By speculatively extracting selected fields from every possible position in each pipeline stage, a correct value may be selected using sequential hardware streaming pipelines to substantially reduce parsing latency.Type: GrantFiled: January 8, 2019Date of Patent: November 28, 2023Assignee: XILINX, INC.Inventors: Jaime Herrera, Gordon J. Brebner, Ian McBryan, Rowan Lyons
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Patent number: 11829733Abstract: Implementing an application for a data processing engine (DPE) array can include detecting, using computer hardware, a component of a hardware library package instantiated by an application. The application is specified in source code and is configured to execute on a DPE array. An instance of the component is extracted from the application. The extracted instance specifies values of parameters for the instance of the component. The instance can be partitioned by generating program code defining one or more kernels corresponding to the instance of the component. The partitioning is based on a defined performance metric of the component and a defined performance requirement of the application. The application is transformed by replacing the instance of the component with the program code generated by the partitioning. The application, as transformed, is compiled into program code executable by the DPE array.Type: GrantFiled: November 22, 2021Date of Patent: November 28, 2023Assignee: Xilinx, Inc.Inventors: Sumanta Datta, Srijan Tiwary, Aman Gayasen
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Publication number: 20230376662Abstract: Methods and systems for simulating RTL models in combination with behavioral models involve generating an overall simulation model from a circuit design by a simulation tool of an EDA system. The overall simulation model includes respective behavioral simulation models of components of the circuit design. A register transfer level (RTL) simulation model of a particular component of the components of the circuit design is generated by an extractor tool of the EDA system. The respective behavioral simulation model of the particular component in the overall simulation model is replaced with the RTL simulation model, and a simulation that executes the overall simulation model and the RTL simulation model in place of the behavioral simulation model of the particular component is performed.Type: ApplicationFiled: May 17, 2022Publication date: November 23, 2023Applicant: Xilinx, Inc.Inventors: Nageshwar Reddy Peddamgari, Sourabh Anand, Vasudha Annam, Chandra Sekhar Mulpuri
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Publication number: 20230376437Abstract: An integrated circuit (IC) can include a data processing array including a plurality of compute tiles arranged in a grid. The IC can include an array interface coupled to the data processing array. The array interface includes a plurality of interface tiles. Each interface tile includes a plurality of direct memory access circuits. The IC can include a network-on-chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via an independent communication channel.Type: ApplicationFiled: May 17, 2022Publication date: November 23, 2023Applicant: Xilinx, Inc.Inventors: David Patrick Clarke, Peter McColgan, Juan J. Noguera Serra, Tim Tuan, Saurabh Mathur, Amarnath Kasibhatla, Javier Cabezas Rodriguez, Pedro Miguel Parola Duarte, Zachary Blaise Dickman
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Patent number: 11824548Abstract: A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a second control signal and selectively connects the voltage supply node to the first path. The second switching circuitry is connected to the second path and a reference voltage node. The second switching circuitry receives the first control signal and the second control signal and selectively connects the reference voltage node to the second path.Type: GrantFiled: December 17, 2021Date of Patent: November 21, 2023Assignee: XILINX, INC.Inventors: Shaojun Ma, Chi Fung Poon
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Patent number: 11824564Abstract: A disclosed compression method includes inputting a data set of floating point values from an input circuit to a compression circuit and detecting non-zero values and sequences of zero values in the data set. The compression circuit outputs, in response to detection of a non-zero value in the data set, the non-zero value to an output circuit. The compression circuit generates, in response to detection of a sequence of zero values in the data set, a subnormal floating point value having significand bits that indicate counted zero values in the sequence, and outputs the subnormal floating point value to the output circuit.Type: GrantFiled: February 9, 2021Date of Patent: November 21, 2023Assignee: XILINX, INC.Inventors: Philip B. James-Roxby, Eric F. Dellinger
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Patent number: 11824761Abstract: Methods and apparatus for detecting alignment markers in received data streams received via a plurality of data lanes are disclosed. Corresponding data streams may be received via respective data lanes in the plurality of data lanes, where each data stream includes alignment markers delineating data frames, and each alignment marker has a predefined bit pattern. For each respective data lane, a determination is made whether a specified portion of the received data stream has at least a threshold degree of similarity with a portion of the predefined bit pattern. In response to determining, for one of the plurality of data lanes, that the specified portion has at least the threshold degree of similarity, a frame boundary may be determined based on the specified portion, and a verification may be performed, that the specified portion of the received data stream corresponds to an alignment marker.Type: GrantFiled: November 26, 2018Date of Patent: November 21, 2023Assignee: Xilinx, Inc.Inventor: Ben J. Jones
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Patent number: 11824534Abstract: A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.Type: GrantFiled: November 16, 2021Date of Patent: November 21, 2023Assignee: XILINX, INC.Inventors: Nakul Narang, Siok Wei Lim, Luhui Chen, Yipeng Wang, Kee Hian Tan
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Patent number: 11824830Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.Type: GrantFiled: April 30, 2021Date of Patent: November 21, 2023Assignee: Xilinx, Inc.Inventors: Steven Leslie Pope, Neil Turton, David James Riddoch, Dmitri Kitariev, Ripduman Sohan, Derek Edward Roberts
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Publication number: 20230370392Abstract: An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths.Type: ApplicationFiled: May 13, 2022Publication date: November 16, 2023Applicant: Xilinx, Inc.Inventors: Krishnan Srinivasan, Sagheer Ahmad, Ygal Arbel, Aman Gupta
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Publication number: 20230367923Abstract: A simulation framework is capable modeling a hardware implementation of a reference software system using models specified in different computer-readable languages. The models correspond to different ones of a plurality of subsystems of the hardware implementation. Input data is provided to a first simulator configured to simulate a first model of a first subsystem of the modeled hardware implementation. The input data is captured from execution of the reference software system. The first simulator executing the first model generates a first data file specifying output of the first subsystem. The first data file specifies intermediate data of the modeled hardware implementation. The first data file is provided to a second simulator configured to simulate a second model of a second subsystem of the modeled hardware implementation. The second simulator executing the second model generates a second data file specifying output of the second subsystem.Type: ApplicationFiled: May 10, 2022Publication date: November 16, 2023Applicant: Xilinx, Inc.Inventors: Ji Yang, Haris Javaid, Sundararajarao Mohan
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Patent number: 11816335Abstract: A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking active states for the regular expression and priorities for the active states by storing the active states of the regular expression in a plurality of priority FIFO memories in decreasing priority order. The system includes a capture engine operating in coordination with the regular expression engine to determine character(s) of the data stream that match the capture sub-expression based on the active state being tracked and decoding the capture entries of the capture table.Type: GrantFiled: April 26, 2022Date of Patent: November 14, 2023Assignee: Xilinx, Inc.Inventors: Sachin Kumawat, David K. Liddell, Paul R. Schumacher
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Publication number: 20230359801Abstract: Routing a circuit design includes generating a graph of the circuit design where each connected component is represented as a vertex, generating a routing solution for the circuit design by routing packet-switched nets so that the packet-switched nets of a same connected component do not overlap, and, for each routing resource that is shared by packet-switched nets of different connected components, indicating the shared routing resource on the graph by adding an edge. Cycle detection may be performed on the graph. For each cycle detected on the graph, the cycle may be broken by deleting the edge from the graph and ripping-up a portion of the routing solution corresponding to the deleted edge. The circuit design, or portion thereof, for which the routing solution was ripped up may be re-routed using an increased cost for a shared routing resource freed from the ripping-up.Type: ApplicationFiled: May 4, 2022Publication date: November 9, 2023Applicant: Xilinx, Inc.Inventors: Sreesan Venkatakrishnan, Nitin Deshmukh, Satish B. Sivaswamy