Patents Assigned to Zarlink Semiconductor V.N. Inc.
  • Patent number: 7277452
    Abstract: A method of updating a lookup table associated with a TDM transmit unit which is coupled to a packet network to receive data therefrom, the lookup table mapping packet network contexts to TDM channels. The method includes priming a controller with data for updating the lookup table in advance of the receipt of packets containing data to which the update relates, incorporating a flag in each packet sent over the packet network to the TDM transmit unit, the flag being set to indicate whether or not a packet is the first packet to which the update relates, and detecting the setting of the flag in a first packet and in response updating the lookup table with the update data.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: October 2, 2007
    Assignee: Zarlink Semiconductor V.N. Inc.
    Inventors: Geoffrey Edward Floyd, Timothy Michael Edmund Frost, James F. Kosolowski, Martin Raymond Scott
  • Patent number: 7257134
    Abstract: A method of synchronizing the information held in a switching database associated with a switching function of a data switching node, with a data network node identifier record associated with a management processor enabling a managed mode thereof is provided. An entry of the switching database is modified. A status specifier corresponding to the modified entry is set to signify the modification thereof. An inspection of the switching database is initiated on the expiration of an adjustable timer, and the information held in modified switching database entries is synchronized with the data network node identifier record. This method of synchronization of the information held in the switching database spreads out of burst changes thereof over time. The advantages are derived from the use of a more economical management processor while providing the same or enhanced levels of service of the data switching node.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: August 14, 2007
    Assignee: Zarlink Semiconductor V.N. Inc.
    Inventors: James Ching-Shau Yik, Eric Lin
  • Publication number: 20070153822
    Abstract: A improved Media Access Control (MAC) module specification is presented. The MAC module specification includes configurable support for: a reduced minimum packet size, a reduced inter-frame-gap size, a reduced preamble, receive and transmit clock generation. Benefits may be derived from protocol overhead reductions. Processors adhering to the improved MAC module specification may exchange information at improved bandwidth efficiencies by directly interconnecting respective MAC modules to one another.
    Type: Application
    Filed: March 16, 2007
    Publication date: July 5, 2007
    Applicant: ZARLINK SEMICONDUCTOR V.N. INC.
    Inventor: Linghsiao Wang
  • Patent number: 7142514
    Abstract: A method of scheduling queue servicing in a data packet switching environment is provided. The method includes a sequence of cyclical steps. The output queues are scheduled for servicing on a least credit value basis. An output queue is selected from a group of output queues associated with a communications port. The selected output port has at least one Payload Data Unit (PDU) pending transmission and a lowest credit value associated therewith. At least one PDU having a length is transmitted from the selected output queue and the credit value is incremented taking the length of the transmitted PDU into consideration. The transmission of PDUs is divided into transmission periods. Once per transmission period credit values associated with output queues holding PDUs pending transmission are decremented in accordance with transmission apportionments assigned for each output queue. The method emulates weighted fair queue servicing with minimal computation enabling hardware implementation thereof.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: November 28, 2006
    Assignee: Zarlink Semiconductor V.N. Inc.
    Inventors: Linghsiao Wang, Craig Barrack, Rong-Feng Chang
  • Patent number: 7142551
    Abstract: Methods and apparatus are presented for scheduling playback for voice data sample packet payloads conveyed over best-effort packet-switched infrastructure. The hardware implementation presented provides support for concurrent and independent comfort noise insertion and for dynamic clock adjustment for telephone sessions provisioned concurrently without making recourse to signaling. The apparatus and methods support high density solutions scaleing up to large numbers of concurrently provisioned telephone sessions.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: November 28, 2006
    Assignee: Zarlink Semiconductor V.N. Inc.
    Inventors: Craig Barrack, James Yik
  • Patent number: 7120683
    Abstract: An architecture for creating a single image for a stack of switches. A plurality of the internetworking devices are provided in a stack configuration for interconnecting networks. Software is executed in each internetworking device such that the stack of internetworking devices appear as a single internetworking device to the interconnected networks.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: October 10, 2006
    Assignee: Zarlink Semiconductor V.N. Inc.
    Inventor: James Ching-Liang Huang
  • Patent number: 7085265
    Abstract: A method of mapping between contexts of a packet network and TDM channels and streams. The method comprises constructing a lookup table defining the sequence in which data is to be mapped between contexts and TDM channels and streams, and including for each row of the table a flag which indicates whether or not that entry is the first entry in the table for the corresponding context. As the TDM receive or transmit entity cycles through the lookup table, use is made of the flags to synchronize the start of each packet with the first entry of a TDM frame for each context.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: August 1, 2006
    Assignee: Zarlink Semiconductor V.N. Inc.
    Inventors: Geoffrey Edward Floyd, Timothy Michael Edmund Frost, James F. Kosolowski, Martin Raymond Scott
  • Patent number: 7082138
    Abstract: A protocol enabling the exchange of information between data switching node components and a supervisory management processor is provided. The protocol defines a data frame format, data fields, data field values of a group of command frames. The exchange of information therebetween via the defined frames enables the production of data switching equipment having a generic implementation with a deployable, upgradeable and expandable feature set providing and enhancing support for current and future services.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: July 25, 2006
    Assignee: Zarlink Semiconductor V.N. Inc.
    Inventors: James Ching-Shau Yik, Linghsiao Wang
  • Patent number: 6999416
    Abstract: A method of utilizing shared memory resources in switching Protocol Data Units (PDUs) at a data switching node is presented. The method includes reserving: a temporary memory storage portion for storing PDUs prior to queuing for processing thereof, a Class-of-Service memory storage portion to provide support Quality-of-Service guarantees, a shared memory-pool portion and an input port memory storage portion enabling non-blocking input port flow control. Provisions are made for PDU discard decisions to be delayed until after PDU headers are inspected subsequent to the receipt of each PDU. Provisions are made for well-behaved data flows conveyed via an input port to be protected against blocking from misbehaving data flows conveyed via other input ports of the data switching node.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: February 14, 2006
    Assignee: Zarlink Semiconductor V.N. Inc.
    Inventors: Linghsiao Wang, Craig Barrack, Rong-Feng Chang
  • Patent number: 6990529
    Abstract: A frame forwarding and discard architecture in a Differentiated Services network environment. The architecture comprises a discard logic for discarding a frame from a stream of incoming frames of the network environment in accordance with a discard algorithm, the frame being discarded if a predetermined congestion level in the network environment has been reached, and a predetermined backlog limit of a queue associated with the frame, has been reached. Scheduling logic is also provided for scheduling the order in which to transmit one or more enqueued frames of the network environment.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: January 24, 2006
    Assignee: Zarlink Semiconductor V.N., Inc.
    Inventors: Brian Yang, Craig I. Barrack, Linghsiao Wang
  • Patent number: 6954424
    Abstract: A credit-based pacing scheme for heterogeneous speed frame forwarding. A control logic controls the transmission of data between a source device and a destination device in accordance with a handshaking protocol. Pacing logic paces the transmission of the data from the source device to the destination device to prevent congestion in the switching fabric. A credit scheme is used to arbitrate among multiple pacing modules per device, each forwarding data at a different rate.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: October 11, 2005
    Assignee: Zarlink Semiconductor V.N., Inc.
    Inventors: Craig I. Barrack, Brian Yang, John Lam, Rong-Feng Chang
  • Patent number: 6868095
    Abstract: A system and method for implementing a control channel in a packet switched communications network. In a computer network, such as a local area network (LAN) it is known to utilize the Ethernet for distributing communications between stations. The Ethernet employs a standard frame format that includes header frames and, in particular a preamble frame which may be used to provide synchronization information between switching devices or nodes. The preamble frame is not required in a Gigabit Ethernet implementation and the present invention employs a portion of the preamble frame to implement a control channel between switching devices.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: March 15, 2005
    Assignee: Zarlink Semiconductor V.N. Inc.
    Inventors: Linghsiao Wang, Craig Barrack, Rong-Feng Chang
  • Publication number: 20040205292
    Abstract: A Ternary/Content Addressable Memory (T/CAM) design is presented. The CAM includes a rule table implemented using a Random Access Module (RAM) storing n rule entries. An n-to-1 multiplexer module, responsive to a value C of a cycle counter, varying between 0 to n-1, provides a selected C'th rule entry to a comparator block which performs a comparison between the selected C'th rule entry and a matching key. The resulting comparison result together with the value C are used to decode the matched rule. In implementing a TCAM, a bitmask table implemented using a RAM module storing n bitmask entries is used. An n-to-1 multiplexer module, responsive to the value C provides a corresponding C'th bitmask to a masking module which modifies the comparison result to ignore a subgroup of results of bitwise comparisons between the C'th rule entry and the matching key.
    Type: Application
    Filed: March 31, 2003
    Publication date: October 14, 2004
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventor: RayChin Lu
  • Patent number: 6799232
    Abstract: A physical interface card for connection to a data bus associated with a data network node is provided. The physical interface card is adapted to perform without supervision from other data bus connected devices: byte ordering, byte alignment and byte scattering/gathering in conveying data between a data bus connected central memory block and at least one data channel associated with the physical interface card. The functionality is provided via a special function direct memory address device operating in accordance with byte ordering specifications for: data stored in the shared memory block and data conveyed via the at least one data channel. The byte alignment is enabled by direct byte addressing techniques as well as the use of an orphan counter to keep track of processed bytes. An implementation of the orphan counter as a state machine reduces processing overheads.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: September 28, 2004
    Assignee: Zarlink Semiconductor V.N., Inc.
    Inventor: Yi-Wen Wang
  • Publication number: 20040170163
    Abstract: Data structures for efficient tracking Real-Time Control Protocol (RTCP) statistical information reported in connection with a Real-Time Protocol (RTP) encapsulated data stream, and a signaling protocol for updating corresponding statistical information between a hardware statistics information collection function and a software statistics information processing function is presented. Hardware data structure and software data structure specifications take into account: the arrival rate of RTCP statistics reports, the rate of generation of RTP packets, expected communication session duration, statistics information processing bandwidth, etc.; to provide a balance between hardware statistics information tracking, timely update of statistics information processed by software, while reducing statistics information update overheads in support of high density data streaming solutions.
    Type: Application
    Filed: February 28, 2003
    Publication date: September 2, 2004
    Applicant: ZARLINK SEMICONDUCTOR V.N. INC.
    Inventors: James Yik, Lijen Ko
  • Patent number: 6775722
    Abstract: An architecture for data retrieval from a plurality of coupling queues. At least first and second data queues are provided for receiving data thereinto. The data is read from the at least first and second data queues with reading logic, the reading logic reading the data according to a predetermined queue selection algorithm. The data read from by reading logic and forwarded to an output queue.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: August 10, 2004
    Assignee: Zarlink Semiconductor V. N. Inc.
    Inventors: David Wu, Jerry Kuo
  • Publication number: 20040151184
    Abstract: Apparatus and methods of providing rate control at a user access point of an edge network node of a packet switched communications network are described. Rate control mechanisms are presented in respect of both ingress and egress rate control with quality of service support. Multiple thresholds associated with a single leaky bucket per traffic flow direction enable the mechanism to selectively control traffic rates based on a traffic class priority criteria.
    Type: Application
    Filed: December 5, 2003
    Publication date: August 5, 2004
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventors: Linghsiao Wang, Craig Barrack
  • Publication number: 20040114616
    Abstract: An improved combined Switching Data Unit (SDU) queuing discipline for unicast and multicast (Protocol Data Unit) PDU forwarding at a switching node is provided. Multicast SDU descriptor pointers are replicated stored in entries of a First-In/First-Out queue portion of a hybrid output port queue. Unicast SDU descriptor pointers are chained in entries of a linked list queue portion of the hybrid output port queue. Servicing of the hybrid queue uses hybrid queue counters, and inter-departure-counters stored in multicast FIFO queue entries to keep track of the number of unicast SDU linked list entries to be services between the multicast FIFO queue entries. The combined hybrid queue derives storage efficiency benefits from linking unicast PDUs in linked lists and further derives benefits from a simple access to multicast PDU entries.
    Type: Application
    Filed: December 13, 2002
    Publication date: June 17, 2004
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventor: Linghsiao Wang
  • Publication number: 20040085910
    Abstract: A improved Media Access Control (MAC) module specification is presented. The MAC module specification includes configurable support for: a reduced minimum packet size, a reduced inter-frame-gap size, a reduced preamble, receive and transmit clock generation. Benefits may be derived from protocol overhead reductions. Processors adhering to the improved MAC module specification may exchange information at improved bandwidth efficiencies by directly interconnecting respective MAC modules to one another.
    Type: Application
    Filed: November 1, 2002
    Publication date: May 6, 2004
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventor: Linghsiao Wang
  • Patent number: 6697873
    Abstract: Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary MAC address table and secondary MAC address table both for storing and searching MAC addresses. The primary table stores records that contain compressed values of MAC addresses. The records are contained in storage locations that are referenced using the compressed value of the MAC address as a search index. In order to account for searching collisions that may result from different MAC addresses compressing to the same value, each record in the primary address table is linked to a chain of records in the secondary table. The records in the secondary table store the full value of the MAC address. Each chain of records in the secondary address table contains MAC addresses the present invention.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: February 24, 2004
    Assignee: Zarlink Semiconductor V.N., Inc.
    Inventors: James Yik, Linghsiao Wang