Patents Assigned to Zarlink Semiconductor V.N. Inc.
  • Publication number: 20040008715
    Abstract: Methods and apparatus are presented for scheduling playback for voice data sample packet payloads conveyed over best-effort packet-switched infrastructure. The hardware implementation presented provides support for concurrent and independent comfort noise insertion and for dynamic clock adjustment for telephone sessions provisioned concurrently without making recourse to signaling. The apparatus and methods support high density solutions scaleing up to large numbers of concurrently provisioned telephone sessions.
    Type: Application
    Filed: July 15, 2002
    Publication date: January 15, 2004
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventors: Craig Barrack, James Yik
  • Publication number: 20040001494
    Abstract: Architecture for generating a playback time from a AAL2 SSCS voice packet sequence number in a stream-based application. The architecture comprises an event scheduler engine for initiating control parameters for an interpretive window associated with a packet stream; a sliding window engine for controlling the interpretive window according to the control parameters; and an arrival engine that maps the packet sequence number to an expected playback time in accordance with an association created between the packet sequence number and the expected playback time by the interpretive window.
    Type: Application
    Filed: July 1, 2002
    Publication date: January 1, 2004
    Applicant: Zarlink Semiconductor V.N. Inc
    Inventors: Craig I. Barrack, James Yik
  • Publication number: 20030179780
    Abstract: A method of and apparatus for detecting drift between two clocks is presented. The apparatus comprises a hardware implementation of a clock drift evaluator. The evaluator monitors received packets associated with a data stream, and extracts a time stamp generated by a source clock from each packet. A difference d between the extracted time stamp and the local time is compared against a d_ref value to determine whether the packet was received early or late. On a prescribed schedule, the degree of late and early receipt of packets is compared against a tolerance level to determine whether a relative drift exists between the pacing of the source clock and the pacing of the local clock. The detection of drift between the two clocks provides support for service level guarantees in provisioning data streaming services in packet-switched environments.
    Type: Application
    Filed: March 20, 2002
    Publication date: September 25, 2003
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventors: Anthony Walker, Craig Barrack
  • Publication number: 20030163507
    Abstract: A task-based chip-level hardware architecture. The architecture includes a task manager for managing a task with task information, and a task module operatively connected to the task manager for performing the task in accordance with the task information.
    Type: Application
    Filed: February 26, 2002
    Publication date: August 28, 2003
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventors: Rong-Feng Chang, Craig I. Barrack, Linghsiao Wang
  • Publication number: 20030126188
    Abstract: A method and apparatus for processing packets carrying a voice payload are presented. The apparatus provides for the reduction of packet transport overheads by embedding a context switching header within pre-existing data transport protocol headers using spare bits as much as possible. The solution provides configurable support for multi-vendor equipment. Provisions are made for the hardware extraction of the context switching header from the packets as well as for the extraction of packets carrying a voice payload from a stream of packets carrying a mixed data traffic. The hardware extraction is supported using bit masks.
    Type: Application
    Filed: December 27, 2001
    Publication date: July 3, 2003
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventors: D.C. John Ta, Rong-Feng Chang
  • Publication number: 20030076784
    Abstract: Methods and apparatus for evaluating the performance of data switching equipment in processing and conveying, delay, jitter and loss sensitive streams of data are provided. The apparatus includes receive trace records and transmit trace records and the methods include the inspection of the receive and transmit trace records to evaluate the performance of the data switching equipment. The advantages include the availability of an assessment of data transport latencies, data conveyance jitter and data segment loss to enable the provisioning of streaming data services.
    Type: Application
    Filed: October 24, 2001
    Publication date: April 24, 2003
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventors: D.C. John Ta, Jim Kosolowski
  • Publication number: 20030063610
    Abstract: A method of synchronizing the information held in a switching database associated with a switching function of a data switching node, with a data network node identifier record associated with a management processor enabling a managed mode thereof is provided. An entry of the switching database is modified. A status specifier corresponding to the modified entry is set to signify the modification thereof. An inspection of the switching database is initiated on the expiration of an adjustable timer, and the information held in modified switching database entries is synchronized with the data network node identifier record. This method of synchronization of the information held in the switching database spreads out of burst changes thereof over time. The advantages are derived from the use of a more economical management processor while providing the same or enhanced levels of service of the data switching node.
    Type: Application
    Filed: October 3, 2001
    Publication date: April 3, 2003
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventors: James Ching-Shau Yik, Eric Lin
  • Publication number: 20030026246
    Abstract: Architecture for processing routing information in a data network. A set of routing information entries is provided in a routing database of a first storage location. A subset of the routing information entries is created in a second storage location, which subset of the routing information entries are in the structure of an IP tree. Packet routing information of an incoming packet is extracted, which packet routing information includes multiple byte parts. The second storage location is accessed to compare the multiple byte parts of the packet routing information sequentially with respective entries of the subset of routing information entries to determine forwarding information. The subset of routing information in the second location is adjusted dynamically in response to the availability of the packet routing information in the subset of routing information entries.
    Type: Application
    Filed: June 5, 2002
    Publication date: February 6, 2003
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventors: James Huang, Eric Lin, Steven Hsieh, James Yik, Ilya Dorfman, George Cravens
  • Publication number: 20020191606
    Abstract: A communication interface for processing errors between network devices. The communication interface includes an output interface of a first network device for generating output control information and parity information of output information transmitted therefrom, and an error-handling interface of a second network device, which error-handling interface is in operative communication with the output interface to process the output control information and the parity information of the output information by, checking parity of the parity information of the output information received from the first network device, terminating the output information when an error in the parity is detected, and recovering a boundary of the output information when an error in the output control information is detected.
    Type: Application
    Filed: May 9, 2002
    Publication date: December 19, 2002
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventors: Shaofeng Wu, Jerry Kuo, Po-Shen Lai, Jian Jin, Autumn Niu
  • Publication number: 20020167950
    Abstract: A protocol and header format of a network architecture for communication between a plurality of network devices. In particular, the data frame is resolved at the source device to ascertain the data frame type, and the data frame is forwarded with a virtual network identifier and priority information from the source device to a destination device of the network. The forwarded data frame also includes control information.
    Type: Application
    Filed: January 14, 2002
    Publication date: November 14, 2002
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventors: Rong-Feng Chang, John Lam, Po-Shen Lai, Brian Yang
  • Publication number: 20020089983
    Abstract: A network switch includes a plurality of ports, a packet engine for transferring incoming packets to an appropriate outgoing port dependent on a destination address carried in said packet, and a switching database providing switching information to said packet engine, said switching database comprising a low speed main database and a high speed cache, and a controller for transferring switching data between said database and said cache in accordance with a predetermined control policy.
    Type: Application
    Filed: December 12, 2001
    Publication date: July 11, 2002
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventors: Changhwa Lin, Zhong Wen
  • Publication number: 20020039350
    Abstract: A method of utilizing shared memory resources in switching Protocol Data Units (PDUs) at a data switching node is presented. The method includes reserving: a temporary memory storage portion for storing PDUs prior to queuing for processing thereof, a Class-of-Service memory storage portion to provide support Quality-of-Service guarantees, a shared memory-pool portion and an input port memory storage portion enabling non-blocking input port flow control. Provisions are made for PDU discard decisions to be delayed until after PDU headers are inspected subsequent to the receipt of each PDU. Provisions are made for well-behaved data flows conveyed via an input port to be protected against blocking from misbehaving data flows conveyed via other input ports of the data switching node.
    Type: Application
    Filed: August 23, 2001
    Publication date: April 4, 2002
    Applicant: Zarlink Semiconductor V.N. Inc.
    Inventors: Linghsiao Wang, Craig Barrack, Rong-Feng Chang