Abstract: An integrated circuit (IC) die includes a first layer with conductive structures formed in a interlayer dielectric (ILD) material, with a portion of the conductive structures at a first surface of the first layer, a self-alignment layer in contact with non-conductive regions at the first surface of the first layer, a second layer with ILD material in contact with the self-alignment layer and the portion of the conductive structures at the first surface of the first layer, and conductive vias through the self-alignment layer and the second layer in contact with the portion of the conductive structures at the first surface of the first layer. The self-alignment layer may include a first material where the self-alignment layer is in contact with the conductive vias and a second material where the self-alignment layer is not in contact with the conductive vias. Other embodiments are disclosed and claimed.

Abstract: Techniques are described to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater). A semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio with little to no tapering in its sidewall profile, so as to enable densely integrated devices. Furthermore, an etching process may be performed on a gate masking structure used to pattern the location of the gate cuts to ensure that the gate masking structure has low sidewall taper and sufficiently opened enough to expose the underlying gate.

Abstract: A system and method for generating, from a permutation of a first input state, a first output state, a first rate and a first capacity, the first rate including a first portion of the first output state and the first capacity including a second portion of the first output state; storing the first output state; generating a first block of ciphertext data of a first packet from XORing the first rate and a first block of plaintext data of the first packet; generating a permutation of a value of the first block of ciphertext data of the first packet concatenated with the first capacity, and generating a second block of ciphertext data of the first packet from XOR of the permutation of the value of the first block of ciphertext data of the first packet concatenated with the first capacity.

Abstract: A method comprises receiving, from a remote device, an audio/video input signal, identifying one or more objects in the audio/video input signal tagged as a sensitive object, evaluating a set of workload requirements for a set of processing workloads comprising portions of the audio/video input signal, selecting one or more heavy processing workloads in the set of processing workloads to send to a compute service provider, in response to a determination that the one or more heavy processing workloads comprises one or more objects tagged as a sensitive object, encrypting the one or more objects tagged as a sensitive object using a homomorphic encryption protocol to generate a first homomorphically encrypted string, and sending the first homomorphically encrypted string to the compute service provider via a privacy protected communication channel.

Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the

Abstract: An improved AR/VR operation includes receiving, by a server computing device, encrypted AR/VR user data and cleartext metadata associated with the encrypted AR/VR user data from a client computing device; getting server data based at least in part on cleartext metadata; encoding the server data; performing an AR/VR process on the encrypted AR/VR user data and the encoded server data to generate encrypted AR/VR results; and sending the encrypted AR/VR results to the client computing device.

Abstract: Various arrangements for IC devices implementing memory with one access transistor for multiple capacitors are disclosed. An example IC device includes a memory array of M memory units, where each memory unit includes an access transistor and N capacitors coupled to the access transistor. A portion of the capacitors are formed in one or more layers above the access transistor, and a portion of the capacitors are formed in one or more layers below the access transistor. The capacitors in a particular memory unit may be coupled to a single via or to individual vias. In some embodiments, some of the vias are backside vias.

Abstract: Systems and methods include establishing a cryptographically secure communication between an application module and an audio module. The application module is configured to execute on an information-handling machine, and the audio module is coupled to the information-handling machine. The establishment of the cryptographically secure communication may be at least partially facilitated by a mutually trusted module.

Abstract: Apparatuses to synchronize lanes that diverge or threads that drift are disclosed. In one embodiment, a graphics multiprocessor includes a queue having an initial state of groups with a first group having threads of first and second instruction types and a second group having threads of the first and second instruction types. A regroup engine (or regroup circuitry) regroups threads into a third group having threads of the first instruction type and a fourth group having threads of the second instruction type.

Abstract: Embodiments are directed to trusted local memory management in a virtualized GPU. An embodiment of an apparatus includes one or more processors including a trusted execution environment (TEE); a GPU including a trusted agent; and a memory, the memory including GPU local memory, the trusted agent to ensure proper allocation/deallocation of the local memory and verify translations between graphics physical addresses (PAs) and PAs for the apparatus, wherein the local memory is partitioned into protection regions including a protected region and an unprotected region, and wherein the protected region to store a memory permission table maintained by the trusted agent, the memory permission table to include any virtual function assigned to a trusted domain, a per process graphics translation table to translate between graphics virtual address (VA) to graphics guest PA (GPA), and a local memory translation table to translate between graphics GPAs and PAs for the local memory.

Abstract: An example of an integrated circuit may include a first execution cluster, a second execution cluster that is one or more of narrower and shallower as compared to the first execution cluster, and circuitry to selectively steer instructions to the first execution cluster and the second execution cluster based on branch misprediction information. Other embodiments are disclosed and claimed.

Abstract: An example of an apparatus may include a first cache organized as two or more portions, a second cache, and circuitry coupled to the first cache and the second cache to determine a designated portion allocation for data transferred from the first cache to the second cache, and track the designated portion allocation for the data transferred from the first cache to the second cache. Other examples are disclosed and claimed.

Abstract: An integrated circuit die includes a first conductive structure for an input of a capacitively coupled device, a second conductive structure aligned with the first conductive structure for a signal to be capacitively coupled to the input of the capacitively coupled device, a first insulator material disposed between the first conductive structure and the second conductive structure, wherein the first insulator material comprises high gain insulator material, and a cooling structure operable to remove heat from the capacitively coupled device to achieve an operating temperature at or below 0° C. Other embodiments are disclosed and claimed.

Abstract: Technologies for memory management with memory protection extension include a computing device having a processor with one or more protection extensions. The processor may load a logical address including a segment base, effective limit, and effective address and generate a linear address as a function of the logical address with the effective limit as a mask. The processor may switch to a new task described by a task state segment extension. The task state extension may specify a low-latency segmentation mode. The processor may prohibit access to a descriptor in a local descriptor table with a descriptor privilege level lower than the current privilege level of the processor. The computing device may load a secure enclave using secure enclave support of the processor. The secure enclave may load an unsandbox and a sandboxed application in a user privilege level of the processor. Other embodiments are described and claimed.

Abstract: An integrated circuit (IC) die includes a plurality of ferroelectric tunnel junction (FTJ) devices, where at least one FTJ of the plurality of FTJ devices comprises first electrode, a second electrode, ferroelectric material disposed between the first and second electrodes, and interface material disposed between at least one of the first and second electrodes and the ferroelectric material. Other embodiments are disclosed and claimed.

Abstract: Techniques are provided to form semiconductor devices that include one or more gate cuts having a layer of polymer material at edges of the gate cut. The polymer layer may be provided as a byproduct of the etching process used to form the gate cut recess through the gate structure, and can protect any exposed portions of the source or drain regions from certain subsequent processes. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The edges of the gate cut may be lined with a polymer layer that is also on any exposed portions of the source or drain regions that were exposed during the etching process used to form the gate cut recess.

Abstract: Techniques relating to virtual idle loops are described. In an embodiment, decoder circuitry decodes a single instruction. The single instruction includes a field for an identifier of a first source operand, a field for an identifier of a second source operand, a field for an identifier of a destination operand, and a field for an opcode. Execution circuitry executes the decoded instruction according to the opcode to: write the first source operand to a memory location identified by the second source operand; compute an index into a control array based at least in part on the destination operand; and determine whether to exit to a hypervisor of a Virtual Machine (VM) based at least in part on data stored at a location in the control array, wherein the location is to be identified by the computed index. Other embodiments are also disclosed and claimed.

Abstract: An apparatus to facilitate supporting vector multiply add with double accumulator access in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising multiplier circuitry to: receive operands for a matrix multiplication operation, wherein the operands comprising two source matrices to be multiplied as part of the matrix multiplication operation; and issue a multiply and add vector (MADV) instruction for the multiplication operation utilizing a double accumulator access output, wherein the MADV instruction to multiply two vectors of the two source matrices in a single floating point (FP) pipeline of the processor.

Abstract: A processor includes a processing core having a register to store an encoded pointer for a memory address to a memory allocation of a memory, the encoded pointer including a first even odd slot (EOS) bit set to a first value and a second EOS bit set to a second value; and circuitry to receive a memory access request based on the encoded pointer; and in response to determining that the first value matches the second value, perform a memory operation corresponding to the memory access request.

Abstract: Technologies for a hybrid digital/analog processor for a quantum computer are disclosed. In the illustrative embodiment, a hybrid digital/analog processor may be able to process digital instructions as well as analog instructions. The digital instructions may be, e.g., read from or write to memory or registers, perform an arithmetic operation, perform a branch, etc. The analog instructions may be to, e.g., provide an analog voltage to a particular electrode of a qubit, provide an analog pulse to a qubit, measure a reflection of an analog signal from a qubit, etc. The integration of analog operations in the hybrid digital/analog processor can improve performance by, e.g., lowering latency and lowering power usage.

Abstract: Prefetch aware LRU cache replacement policy is described. An example of an apparatus includes one or more processors including a graphic processor, the graphics processor including a load store cache having multiple cache lines (CLs), each including bits for a cache line level (CL level) and one or more sectors for data storage; wherein the graphics processor is to receive one or more data elements for storage in the cache; set a CL level to track each CL receiving data, including setting CL level 1 for a CL receiving data in response to a miss in the cache and setting a CL level 2 for a CL receiving prefetched data in response to a prefetch request, and, upon determining that space is required in the cache to store data, apply a cache replacement policy, the policy being based at least in part on set CL levels for the CLs.

Abstract: An IC device includes a metal layer that includes staggered metal lines. The metal lines are in two or more levels along a direction. There may be one or more metal lines in each level. At least some of the metal lines are aligned along the direction so that widths of the metal lines may be maximized for a given total width of the metal layer. The alignment of the metal lines may be achieved through DSA of a diblock copolymer. The metal layer may be connected to vias in two or more levels. The vias may be also connected to another metal layer or a semiconductor device in a FEOL section of the IC device. A via and the metal line connected to the via may be formed through a same recess and deposition process to eliminate interface between the via and metal line.

Abstract: In one embodiment, a processor includes a cache and a core. The core includes an execution unit and cryptographic computing circuitry to encrypt plaintext data output by the execution unit and store the encrypted data in the cache and decrypt encrypted data accessed from the cache and provide the decrypted data to the execution unit for processing. The encryption and decryption are based on both a stream cipher and a block cipher. In some embodiments, the encryption is based on providing an output of the stream cipher to the block cipher and the decryption is based on providing an output of the block cipher to the stream cipher.

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater, such as 10:1). In an example, a semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The semiconductor region can be, for example, a fin of semiconductor material that extends between a source region and a drain region, or one or more nanowires or nanoribbons of semiconductor material that extend between a source region and a drain region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio so as to enable densely integrated devices.

Abstract: An improved search operation includes receiving, by a server computing device, an encrypted search query and cleartext metadata associated with the encrypted search query from a client computing device; performing a search using the encrypted search query to generate encrypted search results; and sending the encrypted search results to the client computing device.

Abstract: Machine learning models can process a video and generate outputs such as action segmentation assigning portions of the video to a particular action, or action classification assigning an action class for each frame of the video. Some machine learning models can accurately make predictions for short videos but may not be particularly suited for performing action segmentation for long duration, structured videos. An effective machine learning model may include a hybrid architecture involving a temporal convolutional network and a bi-directional graph neural network. The machine learning model can process long duration structured videos by using a temporal convolutional network as a first pass action segmentation model to generate rich, frame-wise features. The frame-wise features can be converted into a graph having forward edges and backward edges. A graph neural network can process the graph to refine a final fine-grain per-frame action prediction.

Abstract: Systems, apparatuses and methods may provide for technology that processes an inference workload in a first subset of layers of a neural network that prevents or inhibits data dependent branch operations, conducts an exit determination as to whether an output of the first subset of layers satisfies one or more exit criteria, and selectively bypasses processing of the output in a second subset of layers of the neural network based on the exit determination. The technology may also speculatively initiate the processing of the output in the second subset of layers while the exit determination is pending. Additionally, when the inference workloads include a plurality of batches, the technology may mask one or more of the plurality of batches from processing in the second subset of layers.

Abstract: An integrated circuit (IC) die includes a substrate and an array of memory cells formed in or on the substrate with a memory cell of the array of memory cells that includes a storage circuit that comprises a hysteretic-oxide material. A ternary content-addressable memory (TCAM) may utilize hysteretic-oxide memory cells. Other embodiments are disclosed and claimed.

Abstract: A mechanism is described for facilitating real-time multi-view detection of objects in multi-camera environments, according to one embodiment. A method of embodiments, as described herein, includes mapping first lines associated with objects to a ground plane; and forming clusters of second lines corresponding to the first lines such that an intersection point in a cluster represents a position of an object on the ground plane.

Abstract: An embodiment of a capacitor in the back-side layers of an IC die may comprise any type of solid-state electrolyte material disposed between electrodes of the capacitor. Another embodiment of a capacitor anywhere in an IC die may include one or more materials selected from the group of indium oxide, indium nitride, gallium oxide, gallium nitride, zinc oxide, zinc nitride, tungsten oxide, tungsten nitride, tin oxide, tin nitride, nickel oxide, nickel nitride, niobium oxide, niobium nitride, cobalt oxide, and cobalt nitride between electrodes of the capacitor. Other embodiments are disclosed and claimed.

Abstract: This disclosure describes systems, methods, and devices related to traffic indication map (TIM) piggybacking. A device may determine a frame including one or more TIMs indicating that the device has data to send in a first frequency band of a plurality of supported frequency bands. The device may cause to send the frame in a second frequency band of the plurality of supported frequency bands, wherein the first frequency band is different from the second frequency band, wherein the frame indicates a request for a first station device to be awake in the first frequency band to receive the data. The device may cause to send the data using the first frequency band.

Abstract: IC devices with angled interconnects are disclosed herein. An interconnect, specifically a trench or line interconnect, is referred to as an “angled interconnect” if the interconnect is neither perpendicular nor parallel to any edges of front or back faces of the support structure, or if the interconnect is not parallel or perpendicular to interconnect in another region of an interconnect layer. Angled interconnects may be used to decrease the area of pitch transition regions. Angled interconnects may also be used to decrease the area of pitch offset regions.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a conductive pad having a first surface and an opposing second surface; a conductive via coupled to the first surface of the conductive pad; a microelectronic component having a conductive contact, the conductive contact of the microelectronic component electrically coupled, by an interconnect, to the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin; and a liner between the interconnect and the second surface of the conductive pad, and wherein a material of the liner includes nickel, palladium, or gold. In some embodiments, a bottom surface of the liner is curved outward towards the conductive pad. In some embodiments, the liner also may be on side surfaces of the interconnect.

Abstract: An embodiment of an integrated circuit (IC) device may include a plurality of layers of wide bandgap (WBG)-based circuitry and a plurality of layers of silicon (Si)-based circuitry monolithically bonded to the plurality of layers of WBG-based circuitry, with one or more electrical connections between respective WBG-based circuits in the plurality of layers of WBG-based circuitry and Si-based circuits in the plurality of layers of Si-based circuitry. In some embodiments, a wafer-scale WBG-based IC is hybrid bonded or layer transfer bonded to a wafer-scale Si-based IC. Other embodiments are disclosed and claimed.

Abstract: Disclosed herein are integrated circuit (IC) devices with contacts using nitridized molybdenum. For example, a contact arrangement for an IC device may include a semiconductor material and a contact extending into a portion of the semiconductor material. The contact may include molybdenum. The molybdenum may be in a first layer and a second layer, where the second layer may further include nitrogen. The first layer may have a thickness between about 5 nanometers and 16 nanometers, and the second layer may have a thickness between about 0.5 nanometers to 2.5 nanometers. The contact may further include a fill material (e.g., an electrically conductive material) and the second layer may be in contact with the fill material. The molybdenum may have a low resistance, and thus may improve the electrical performance of the contact. The nitridized molybdenum may prevent oxidation during the fabrication of the contact.

Abstract: An integrated circuit device includes a first IC die with a first front surface, a first back surface, and a first side surface along opposed edges of the first front surface and the first back surfaces of the first IC die, a second IC die with a second front surface, a second back surface, and a second side surface along opposed edges of the second front surface and second back surface of the second IC die, a substrate coupled to the first side surface of the first IC die and the second side surface of the second IC die, and fill material between one of the first front surface and the first back surface of the first IC die and one of the second front surface and second back surface of the second IC die. Other embodiments are disclosed and claimed.

Abstract: An integrated circuit (IC) die includes a plurality of varactor devices, where at least one varactor of the plurality of varactor devices comprises a first electrode, a second electrode, and a multi-layer stack of ferroelectric material (e.g., ferroelectric variable capacitance material) disposed between the first and second electrodes. Other embodiments are disclosed and claimed.

Abstract: Methods for fabricating an integrated circuit (IC) device with a protection liner between doped semiconductor regions are provided. An example IC device includes a channel material having a first face and a second face opposite the first face, a first doped region and a second doped region in the channel material, extending from the second face towards the first face by a first distance; and an insulator structure in a portion of the channel material between the first and second doped regions, the insulator structure extending from the second face towards the first face by a second distance greater than the first distance. The insulator structure includes a first portion between the second face and the first distance and a second portion between first distance and the second distance. The insulator structure includes a liner material on sidewalls of the first portion but absent on sidewalls of the second portion.

Abstract: Top-gate thin film transistor (TFTs) structures. Thin film transistors when in the top-gate configuration suffer from contact resistance. An example TFT includes a semiconductor layer doped with one or more dopant elements. A gate dielectric layer is on the semiconductor layer, and a gate electrode is on the gate dielectric layer. The semiconductor layer is doped with the one or more dopant elements beneath the gate dielectric layer. The TFT may further include one or more contacts and/or one or more gate spacers, and the semiconductor layer may further be doped with the one or more dopant elements beneath the contact(s) and/or gate spacer(s).

Abstract: A system and method of enhancing the mitigation of side channel attacks on platform interconnects using endpoint HW based detection, synchronization, and re-keying include generating a set of keys for link encryption based on a high entropy seed, storing the set of keys in a deterministic order in a register, detecting that a re-key programmable threshold is met during link encryption with a device, identifying a synchronization point associated with the device, where the synchronization point indicates the device is ready to switch a current key used for link encryption, and synchronizing a rekeying event with the device.

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

Abstract: Methods, articles, and systems of image processing comprise obtaining image data of frames of a video sequence. The method also includes determining multiple reference frames of a current frame in the video sequence. The multiple reference frames each have at least one motion compensated (MC) block of image data. Also, the method then includes generating a weight that factors noise, distortion variance, and dispersion distribution between the same MC block position and the current block. Thereafter, the method includes generating denoised filtered image data comprising applying one of the weights to the image data of the motion compensated (MC) block.

Abstract: Described are precursor compounds and methods for atomic layer deposition of films containing scandium(III) oxide or scandium(III) sulfide. Such films may be utilized as dielectric layers in semiconductor manufacturing processes, particular for depositing dielectric films and the use of such films in various electronic devices.

Abstract: An IC device includes a transistor, a first layer, and a second layer. The first layer is coupled to the transistors and is between the transistor and the second layer in a first direction. The first layer includes a first structure and a second structure. The first structure includes a first metal (e.g., Ru). The second structure includes a second metal (e.g., Cu). The second structure may be wrapped around by a different material that may include a third metal (e.g., Co). The first structure may be shorter than the second structure in the first direction and narrower than the second structure in a second direction orthogonal to the first direction. The first structure may be closer to the second layer than the second structure in the first direction. The first structure may be a wordline of a memory. The second structure may be a bitline.

Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to semiconductor interconnects, such as on-package die-to-die (D2D) interconnects, for example. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

Abstract: Hybrid manufacturing of access transistors for memory, presented herein, explores how IC components fabricated by different manufacturers may be combined in an IC device to achieve advantages in terms of, e.g., performance, density, number of active memory layers, fabrication approaches, and so on. In one aspect, an IC device may include a support, a first circuit over a first portion of the support, a second circuit over a second portion of the support, a scribe line between the first circuit and the second circuit, and one or more electrical traces extending over the scribe line. In another aspect, an IC device may include a support, a memory array, comprising a first circuit over a first portion of the support and one or more layers of capacitors over the first circuit, and a second circuit over a second portion of the support.

Abstract: A circuit system includes a support device having an interconnection conductor. The circuit system also includes first, second, and third integrated circuits that are mounted on the support device. The interconnection conductor couples the first integrated circuit to the third integrated circuit. The second integrated circuit is between the first integrated circuit and the third integrated circuit.

Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.

Abstract: This disclosure describes systems, methods, and devices related to enhanced L-SIG. A device may generate a frame for 60 gigahertz (GHz) transmission, the frame comprising one or more fields to carry information associated with one or more station devices (STAs). The device may generate a special legacy signal (L-SIG) field comprising one or more subfields for operation in the 60 gigahertz (GHz) transmission. The device may include the L-SIG field in the frame. The device may cause to send the frame to the one or more STAs.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein.