Abstract: Disclosed examples include after a first tuning of hyperparameters in a hyperparameter space, selecting first hyperparameter values for respective ones of the hyperparameters; generating a polygonal shaped failure region in the hyperparameter space based on the first hyperparameter values; setting the first hyperparameter values to failure before a second tuning of the hyperparameters; and selecting second hyperparameter values for the respective ones of the hyperparameters in a second tuning region after the second tuning of the hyperparameters in the second tuning region, the second tuning region separate from the polygonal shaped failure region.

Abstract: An apparatus for encoding and decoding video receives a request to decode a current video frame. The apparatus determines whether encoding is within a threshold for a previous video frame. Additionally, the apparatus waits for the encoding to start if the encoding is within the threshold. Further, the apparatus provides a signal to begin encoding the current video frame. Also, the apparatus submits a decode workload to a graphics processor unit (GPU) for the current video frame. The apparatus additionally submits, in parallel with submitting the decode workload to the GPU, an encode workload to the GPU for the previous video frame.

Abstract: Examples described herein relate to a graphics processing apparatus that includes a memory device and a graphics processing unit (GPU). In some examples, the GPU is configured to execute a shader program that is to identify at least two code blocks that are independent from each other and cause execution of an unexecuted independent code block with available data based on use of a scoreboard to track data availability for independent code blocks. In some examples, execution of the shader program is to cause the GPU to select a first code block identifier for tracking completion of a dependency of the first independent code block. In some examples, execution of the shader program is to cause the GPU to identify an offset to a first instruction position in a sequence of instructions of the first independent code block in an instruction queue.

Abstract: Apparatus and methods for thermal management of electronic user devices are disclosed herein. An example apparatus includes at least one of a user presence detection analyzer to identify a presence of a user relative to an electronic device based on first sensor data generated by a first sensor or at least one of an image data analyzer or a motion data analyzer to determine a gesture of the user relative to the device based on second sensor data generated by a second sensor; a thermal constraint selector to select a thermal constraint for a temperature of an exterior surface of the electronic device based on one or more of the presence of the user or the gesture; and a power source manager to adjust a power level for a processor of the electronic device based on the thermal constraint.

Abstract: A method for trajectory generation based on player tracking is described herein. The method includes determining a temporal association for a first player in a captured field of view and determining a spatial association for the first player. The method also includes deriving a global player identification based on the temporal association and the spatial association and generating a trajectory based on the global player identification.

Abstract: A device to host a service producer in a 5G system (or 5G system architecture), a method to be performed at the device, and a non-transitory storage device storing instructions to be executed at the device. The method includes: decoding a request from a service consumer to manage one or more 5G quality of service (QoS) indicators (5QIs), each 5QI including a 5QI value and corresponding 5QI characteristics; configuring one or more network functions (NFs) of the 5GS with the 5QIs based on the request; and encoding for transmission to the service consumer a message including a result of managing the one or more 5QIs.

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

Abstract: Methods, systems, and storage media are described for monitoring downlink control information (DCI). In particular, some embodiments may be directed to monitoring DCI for an indication of channel occupancy time (COT) information. Other embodiments may be described and/or claimed.

Abstract: The computer executable instructions include a command that accepts multiple user input through various command options. The command encapsulates and implements multiple original software algorithms that convert trunking design intent, expressed via the command options, into trunks on multiple layers of a process technology node. Once executed, the command generates shapes of trunks of specified topology on specified layers. The command includes a set of options to generate a simple or complex trunking topology. The command accepts topology, set of zones, nets and many other options that the user provides to the command to yield trunks of a desired topology. The topology description is relative; thus, it can easily adjust as design changes. The command together with its options represents trunk creation intent.

Abstract: Systems, apparatuses, and methods to mitigate effects of glitch attacks on a broadcast communication bus are provided. The voltage levels of the communication bus are repeatedly sampled to identify glitch attacks. The voltage level on the communication bus can be overdriven or overwritten to either corrupt received messages or correct received messages.

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Abstract: Methods, apparatus, systems and articles of manufacture to identify a side-channel attack are disclosed. Example instructions cause one or more processors to generate an event vector based on one or more counts corresponding to tasks performed by a central processing unit; determine distances between the event vector and weight vectors of neurons in a self-organizing map; select a neuron of the neurons that results based on a determined distance; identify neurons that neighbor the selected neuron; and update at least one of a weight vector of the selected neuron or weight vectors of the neighboring neurons based on the determined distance of the selected neuron.

Abstract: Methods, apparatus, systems and articles of manufacture for distributed training of a neural network are disclosed. An example apparatus includes a neural network trainer to select a plurality of training data items from a training data set based on a toggle rate of each item in the training data set. A neural network parameter memory is to store neural network training parameters. A neural network processor is to generate training data results from distributed training over multiple nodes of the neural network using the selected training data items and the neural network training parameters. The neural network trainer is to synchronize the training data results and to update the neural network training parameters.

Abstract: Examples described herein relate to processor circuitry to issue a cache coherence message to a central processing unit (CPU) cluster by selection of a target cluster and issuance of the request to the target cluster, wherein the target cluster comprises the cluster or the target cluster is directly connected to the cluster. In some examples, the selected target cluster is associated with a minimum number of die boundary traversals. In some examples, the processor circuitry is to read an address range for the cluster to identify the target cluster using a single range check over memory regions including local and remote clusters. In some examples, issuance of the cache coherence message to a cluster is to cause the cache coherence message to traverse one or more die interconnections to reach the target cluster.

Abstract: Systems, methods, and apparatuses relating to linear address masking architecture are described. In one embodiment, a hardware processor includes an address generation unit to generate a linear address for a memory access request to a memory, at least one control register comprising a user mode masking bit and a supervisor mode masking bit, a register comprising a current privilege level indication, and a memory management unit to mask out a proper subset of bits inside an address space of the linear address for the memory access request based on the current privilege level indication and either of the user mode masking bit or the supervisor mode masking bit to produce a resultant linear address, and output the resultant linear address.

Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.

Abstract: Apparatuses, methods and storage medium associated with multi-camera devices are disclosed herein. In embodiments, a multi-camera device may include 3 or more camera sensors disposed on a world facing side of the multi-camera device. Further, the multi-camera device may be configured to provide a soft shutter button at a location on an opposite side to the world facing side, coordinated with locations of the 3 or more camera sensors that reduces likelihood of blocking of one or more of the 3 or more camera sensors. Other embodiments may be disclosed or claimed.

Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.

Abstract: Systems, apparatuses and methods may provide for a frontend driver that notifies a hypervisor of a map request from a guest driver of a device, wherein the device is passed through to and directly controlled by a virtual machine, and wherein the map request is associated with an attempt of the device to access a guest memory page in a virtualized execution environment. The frontend driver may also determine whether the guest memory page is pinned and send a map hypercall to the hypervisor if the guest memory page is not pinned. Additionally, the hypervisor may determine that the guest memory page is pinned, determine, based on a direct memory access (DMA) bitmap, that an unmap request from the guest driver has been issued, and unpin the guest memory page.

Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.

Abstract: Described herein is a cloud-based gaming system in which graphics processing operations of a cloud-based game can be performed on a client device. Client-based graphics processing can be enabled in response to a determination that the client includes a graphics processor having a performance that exceeds a minimum threshold. When a game is remotely executed and streamed to a client, the client is configurable to provide network feedback that can be used to adjust execution and/or encoding for the game.

Abstract: Techniques related to packing pieces of data having variable bit lengths to serial packed data using a graphics processing unit and a central processing unit are discussed. Such techniques include executing bit shift operations for the pieces of data in parallel via execution units of the graphics processing unit and packing the bit shifted pieces of data via the central processing unit.

Abstract: Processor trace systems and methods are described. For example, one embodiment comprises executing instrumented code by a compiler, the instrumented code including at least one call to un-instrumented code. The compiler can determine the at least one call to un-instrumented code is a next call to be executed. A resume tracing instruction can be inserted into the instrumented code prior to the at least one call to the un-instrumented code. The resume tracing instruction can be executed to selectively add processor tracing to the at least one call to the un-instrumented code, and the at least one call to the un-instrumented code can be executed.

Abstract: In an embodiment, a processor comprises: an execution circuit to execute instructions; at least one cache memory coupled to the execution circuit; and a table storage element coupled to the at least one cache memory, the table storage element to store a plurality of entries each to store object metadata of an object used in a code sequence. The processor is to use the object metadata to provide user space multi-object transactional atomic operation of the code sequence. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus comprises circuitry, wherein the circuitry is configured to: receive, via a communications network, context information for a first set of one or more edge devices, wherein the context information identifies an operating environment of the first set of edge devices based on information from one or more sensors; receive, via the communications network, workload information for a second set of one or more edge devices; determine workload assignments for the first set of edge devices based on the context information for the first set of edge devices and based on the workload information for the second set of edge devices; and transmit, via the communications network, the workload assignments to the first set of edge devices.

Abstract: Folded integer multiplier (FIM) circuitry includes a multiplier configurable to perform multiplication and a first addition/subtraction unit and a second addition/subtraction unit both configurable to perform addition and subtraction. The FIM circuitry is configurable to determine each product of a plurality of products for a plurality of pairs of input values having a first number of bits by performing, using the first and second addition/subtraction units, a plurality of operations involving addition or subtraction, and performing, using the multiplier, a plurality of multiplication operations involving values having fewer bits than the first number of bits. The plurality of multiplication operations includes a first number of multiplication operations, and the multiplier is configurable to begin performing all multiplication operations of the plurality of multiplication operations within a first number of clock cycles equal to the first number of multiplication operations.

Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices.

Abstract: An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.

Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. A quasi-delay insensitive (QDI) shift register and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.

Abstract: Various embodiments generally may relate to Load Balancing Optimization (LBO) and Mobility Robustness Optimization (MRO). Some embodiments of this disclosure are directed to the following 5G SON solutions: use cases and requirements for the management of distributed LBO and centralized LBO; procedures for the management of distributed LBO and centralized LBO; and management services and information needed to support the management of distributed LBO and centralized LBO.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.

Abstract: A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.

Abstract: Techniques are provided for detection of laser-based audio injection attacks. A methodology implementing the techniques according to an embodiment includes calculating cross correlations between signals received from microphones of an array of two or more microphones. The method also includes identifying time delays associated with peaks of the cross correlations, and magnitudes associated with the peaks of the cross correlations. The method further includes calculating a time alignment metric based on the time delays and calculating a similarity metric based on the magnitudes. The method further includes generating a first attack indicator based on a comparison of the time alignment metric to a first threshold and generating a second attack indicator based on a comparison of the similarity metric to a second threshold. The method further includes providing warning of a laser-based audio attack based on the first attack indicator and/or the second attack indicator.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a sandwich plate construction heatsink. The sandwich plate construction heatsink can include a cold plate, one or more heat pipes over the cold plate, and a top plate over the one or more heat pipes. The cold plate can include a channel to accommodate the one or more heat pipes and/or the top plate can include a channel to accommodate the one or more heat pipes. The cold plate can be over a heat source in the electronic device.

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

Abstract: Technologies for fast boot-up of a compute device with error-correcting code (ECC) memory are disclosed. A basic input/output system (BIOS) of a compute device may assign memory addresses of the ECC memory to different processors on the compute device. The processors may then initialize the ECC memory in parallel by writing to the ECC memory. The processors may write to the ECC memory with direct-store operations that are immediately written to the ECC memory instead of being cached. The BIOS may continue to operation on one processor while the rest of the processors initialize the ECC memory.

Abstract: An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.

Abstract: Methods, systems and apparatuses may provide for technology that triggers an idle state in a first command streamer in response to a request to reset a second command streamer that shares graphics hardware with the first command streamer. The technology may also determine an event type associated with the request and conduct the request based on the event type.

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform multi-rate shading via coarse pixel shading and output shaded coarse pixels for processing by a post-shader pixel processing pipeline.

Abstract: An extremely high-throughput (EHT) station (STA) may encode an EHT PPDU for transmission on a plurality of subchannels. The EHT STA may determine a spectral mask to apply to the EHT PPDU prior to transmission of the EHT PPDU. When preamble puncturing is performed, the EHT STA may apply an overall spectral mask to the EHT PPDU prior to transmission. The overall spectral mask may be based on an interim spectral mask and a preamble-puncture spectral mask. The subchannels may be in a 6 GHz band and the EHT STA may determine if preamble puncturing is to be performed for one or more of the subchannels based on a presence of incumbents in the one or more of the subchannels, although the scope of the embodiments is not limited in this respect.

Abstract: A computer-readable storage medium stores instructions for execution by one or more processors of a UE. The instructions configure the UE for small data transmission (SDT) in a 5G NR network and cause the UE to perform operations comprising detecting while in an RRC_Inactive state, a radio link failure during a first SDT of UL data to a base station. A secure key for a second SDT is generated based on the radio link failure. A configuration message including an indication of the second SDT is transmitted to the base station. A response message including a UL grant is received from the base station. The UL data is encoded for the second SDT using the secure key. The second SDT is performed using the UL grant while the UE is in the RRC_Inactive state.

Abstract: An apparatus and system to enable dynamic offloading and execution of compute tasks are described. In split CU-DU RAN architectures, the CU-CP is connected with multiple compute control functions (CF) and service functions (SF) that have different computing hardware/software capabilities. Different architectures depend on whether the SF is collocated with the CU-UP, the CU-UP and SF only serve compute messages, a compute message is supplied directly to the CU-UP or also traverses the CU-CP. In response to reception from a UE of a compute message containing data for computation being sent to the CU-CP through the DU, the CU-CP sends the data to the SF with identifiers and sends the result to the UE.

Abstract: Disclosed embodiments provide a handover prediction scheme that is based on contextual awareness of a compute node, such as a mobile device. The contextual information is used to predict network availability in a predicted target location, which is an area that a compute node is likely to travel. The use of sensors embedded in or accessible by the compute node may be used to carry out aspects of the embodiments. A reinforcement learning recommendation model is used to determine an optimal network, radio access technology, and/or network access node to connect with ahead of arriving at the predicted target location at a predicted arrival time. Other embodiments are described and/or claimed.

Abstract: Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.