Abstract: A workflow execution apparatus and workflow execution method for processing distributed processing analysis tasks in a container environment including a user interface (UI) unit configured to receive an input target workflow of an analysis task to be processed, a workflow scheduler configured to retrieve resource templates executable by the target workflow from among a plurality of resource templates, and generate a final workflow by applying a resource configuration corresponding to the retrieved resource template to the target workflow according to a selected template, and a workflow worker configured to request execution of a distributed processing driver in a container environment, reuse a currently executed distributed processing driver when processing each of tasks included in the final workflow, and execute the final workflow.

Abstract: A system for partitioning a keyspace includes: a system for partitioning a keyspace, includes: a server configured to transmit a partition setting item based on a keyspace creation request; and a database configured to receive the partition setting item and configured to create a first partition for the keyspace based on the received partition setting item, wherein the partition setting item includes a replication factor and at least one of a size of a second partition for storing data or a storage period of the data.

Abstract: An apparatus for supporting business transactions including one or more processors configured to execute instructions and a memory storing the instructions, the execution of the instructions configures the one or more processors to receive a business process notification from a business system, the business process notification including one or business notification details and business process details, generate an app card based on the one of the business notification details and the business process notification, and transmit the app card to a messenger server, the app card being transmitted to a user terminal through the messenger server to be displayed using a messenger application of the user terminal and the generation of the app card being performed using standard data obtained by converting the one of the business notification details or the business process details included in the business process notification according to a preset standard format.

Abstract: A server includes a communication interface; and at least one processor operatively connected to the communication interface and configured to: identify, based on use information received through the communication interface and related to at least one from among a plurality of electronic apparatuses, a first electronic apparatus to be used after from among the plurality of electronic apparatuses, and control the communication interface to transmit, to the first electronic apparatus from among the plurality of electronic apparatuses, a first control signal for controlling the first electronic apparatus.

Abstract: A method and device for labeling are provided. A labeling method includes: determining inference performance features of respective neural network models included in an ensemble model, wherein the inference performance features correspond to performance of the neural network models with respect to inferring classes of the ensemble model; based on the inference performance features, determining weights for each of the classes for each of the neural network models, wherein the weights are not weights of nodes of the neural network models; generating classification result data by performing a classification inference operation on labeling target inputs by the neural network models; determining score data representing confidences for each of the classes for the labeling target inputs by applying weights of the weight data to the classification result data; and measuring classification accuracy of the classification operation for the labeling target inputs based on the score data.

Abstract: A robotic process automation (RPA) bot execution optimization method is provided. The method includes installing an RPA agent and a default RPA engine on the computing system in a process of installing an RPA solution; acquiring, by the installed RPA agent, an execution request for an RPA bot; determining, by the installed RPA agent, a representative version of an RPA scenario for the RPA bot; preparing, by the installed RPA agent, an optimal RPA engine version for executing the RPA scenario representative version; and controlling, by the installed RPA agent, the prepared optimal RPA engine version to execute the RPA scenario.

Abstract: An apparatus includes: one or more processors configured to: randomly split a training data set into a first training data set comprising a first label assigned to first data and a second training data set comprising a second label assigned to second data; train a first neural network using a semi-supervised learning scheme based on the first training data set comprising the first label, and an unlabeled second training data set; and train a second neural network using the semi-supervised learning scheme based on the second training data set comprising the second label, and an unlabeled first training data set.

Abstract: The present disclosure relates to a method, an apparatus, a system, and a computer program for managing a software component and, more specifically, to a method, an apparatus, a system, and a computer program for managing several software components such as an operating system and a hypervisor constituting a cloud environment.

Abstract: Provided is a method performed by at least one processor, including: obtaining a content search term, the content search term including a first plurality of search keywords; performing a search for a plurality of contents using the first plurality of search keywords; extracting, based on no result of the search, a second plurality of search keywords from the first plurality of search keywords, wherein the second plurality of search keywords exclude keywords that are not included in a first keyword set, and the first keyword set includes keywords extracted from the plurality of contents; and performing a search for the plurality of contents using the second plurality of search keywords.

Abstract: A display device includes a display unit including a lower substrate and first, second, and third light emitting elements disposed on the lower substrate, a color filter unit including an upper substrate having a lower surface facing the first, second, and third light emitting elements, a filler disposed between the display unit and the color filter unit and including a wavelength conversion particle. The color filter unit further includes a color filter layer including first, second, and third color filters disposed on the lower surface of the upper substrate, a bank layer disposed below the color filter layer and including first, second, and third openings, a first column spacer filling the first opening, and a second column spacer filling the second opening.

Abstract: A system-on-chip includes a processor configured to execute code corresponding to at least one application and a throttling controller configured to generate throttling control information by using a history table storing a plurality of pieces of history utilization information respectively corresponding to a plurality of functions included in the code, the throttling control information controlling throttling of the processor with respect to each of the plurality of functions, and generate a throttling control signal corresponding to the throttling control information.

Abstract: Provided is an electronic device and a method of controlling thereof. The electronic device includes a display, a communicator, a memory, and a processor configured to obtain a plurality of images corresponding to content being provided to the display, based on information corresponding to a preferred content of a user being obtained based on the plurality of images transmitted to a server through the communicator, control the display to provide a user interface (UI) for entering a metaverse space corresponding to the preferred content, and based on a user command for entering the metaverse space being input through the UI, control the display to display a screen based on data corresponding to the metaverse space received from the server through the communicator.

Abstract: An apparatus with region of interest (ROI) extraction includes: a processor configured to: generate an input image by distorting an original image comprising one or more objects; determine, based on the original image, a quality score of the input image using a machine learning model that is trained based on a mean opinion score (MOS) dataset; generate a class activation map for the input image based on the quality score of the input image; and extract an ROI from the original image based on the class activation map.

Abstract: Image alignment is achieved by obtaining a fused optical flow based on a global motion estimate and an optical flow estimate. The fused optical flow may be used to warp the first image and/or the second image into aligned features or aligned images. An output image may then be obtained by combining.

Abstract: A processing element includes an analog operation circuit configured to receive input data from an input buffer and to generate one or more output currents associated with a multiplication operation of the input data and weights based on a bit-precision of stored weights, one or more analog-to-digital converters (ADCs) each configured to convert the one or more output currents into one or more digital codes, and a digital operation circuit configured to perform an addition operation using the one or more digital codes based on the bit-precision of the weight and to perform a summation operation on a resultant value of the addition operation based on a bit-precision of the input data.

Abstract: A method for generating a depth map includes acquiring at least one image of a scene including a reflective object or a semi-transparent object, acquiring, from the at least one image, a first depth map including a depth value for at least one opaque object which is reflected by the reflective object or viewed through the semi-transparent object, acquiring, from the at least one image, a second depth map including a depth value for the reflective object or the semi-transparent object, and generating a depth map for the scene based on the acquired first depth map and the acquired second depth map, and the generated depth map includes the depth value for the reflective object or the semi-transparent object and the depth value for the at least one opaque object which is reflected by the reflective object or viewed through the semi-transparent object.

Abstract: Disclosed is an image processing method including obtaining, from a first image, object information of an important object included in the first image, obtaining control information for image quality processing, and obtaining a second image by performing image quality processing on the important object from the first image based on the object information and user control information.

Abstract: An object tracking apparatus is provided. The object tracking apparatus includes a processor configured to detect, from a first image frame, an amodal region including a first visible region in which a target object is visible and an occlusion region in which the target object is occluded, determine, based on the detected amodal region of the first image frame, that at least a partial region of a second image frame is a search region of the second image frame, the second image frame being temporally adjacent to the first image frame, and track the target object in the second image frame based on the determined search region.

Abstract: A method of training a neural network model to generate a three-dimensional (3D) model of a scene includes: generating the 3D model based on a latent code; based on the 3D model, sampling a camera view including a camera position and a camera angle corresponding to the 3D model of the scene; generating a two-dimensional (2D) image based on the 3D model and the sampled camera view; and training the neural network model to, using the 3D model, generate a scene corresponding to the sampled camera view based on the generated 2D image and a real 2D image.

Abstract: An apparatus for grouping work request contents selected from a work request content list including one or more processors and a memory storing instructions, an execution of the instructions configuring the one or more processors to display a work request content list, the work request content list including work request contents associated with a function for requesting handling by a user are enumerated, receive a user selection of two or more work request contents from among a plurality of work request contents enumerated in the displayed work request content list, and group two or more selected work request contents according to a classification criteria.

Abstract: A processor-implemented method includes: determining a prediction loss based on class prediction data obtained by applying a first machine learning model to a training input and a class label with which the training input is labeled; determining a confidence of the class label based on the determined prediction loss; and training a second machine learning model using the training input based on the determined confidence.

Abstract: A semiconductor package, includes: a base chip having a front surface and a back surface opposite to the front surface, the base chip including bump pads, wafer test pads, and package test pads, disposed on the front surface; connection structures disposed on the front surface of the base chip and connected to the bump pads; and semiconductor chips stacked on the back surface of the base chip, wherein each of the wafer test pads is smaller than the package test pads.

Abstract: A method of manufacturing a multilayer electronic component, the method includes, attaching a margin portion green sheet including a ceramic material, a photocuring agent, and a photoinitiator to at least one end surface of each of the plurality of cut ceramic green sheet stacked bodies in the third direction, an energy irradiation operation of irradiating, with energy, the margin portion green sheet to generate a photocuring polymerization reaction between the photocuring agent and the photoinitiator.

Abstract: The present disclosure provides methods, apparatuses, and computer-readable mediums for performing data augmentation. In some embodiments, a method of performing data augmentation by a device includes obtaining a plurality of images from a dataset. The method further includes computing, for each image of the plurality of images, a corresponding saliency map based on a gradient of a full loss function of that image. The method further includes selecting, from a subset of arrangements of a plurality of possible arrangements, a rearrangement offset that maximizes an overall saliency of a resulting image combining the plurality of images. The method further includes generating, using the rearrangement offset and a plurality of mixing ratios, a new mixed image from the plurality of images and a new mixed label from corresponding labels of the plurality of images. The method further includes augmenting the dataset with the new mixed image and the new mixed label.

Abstract: The disclosure provides computer-implemented method for training a vision-language machine learning, ML, model to classify images depicting novel or known classes. The method comprises obtaining a first training dataset comprising a plurality of class names and training the vision-language ML model. The training method comprises: generating at least one augmented textual prompt; inputting the at least one augmented textual prompt into a frozen text encoder; outputting a first text embedding for each augmented textual prompt; generating a plurality of first inputs by concatenating each learnable soft prompt from a plurality of learnable soft prompts; inputting the class names and the plurality of first inputs into the frozen text encoder; outputting a second text embedding for each first input; and minimizing a cross-entropy text-to-text loss between the first text embeddings and the second text embeddings.

Abstract: A processor-implemented method includes: determining distances between an input vector and center vectors comprised in a plurality of output nodes comprised in a trained codebook; and outputting a first feature vector of the input vector based on the distances between the center vectors and the input vector, wherein the trained codebook is trained by: determining a distance between a training input vector and the center vector for each of the output nodes; determining, among the plurality of output nodes, a best matched unit (BMU) in which a distance between the training input vector and the center vector of the BMU is minimized; and training the codebook by updating the center vector of the BMU, based on the distance between the training input vector and the center vector of the BMU.

Abstract: A cell architecture including at least one semiconductor device cell is provided.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: forming a first structure on a first wafer; forming a second structure on a second wafer including second chip regions and a second scribe lane region surrounding the second chip regions; separating first ones of the second chip regions in a central portion of the second wafer in a plan view by a first dicing process; bonding the first ones of the second chip regions with the first wafer; separating second ones of the second chip regions in an edge portion of the second wafer in a plan view by a second dicing process; bonding the second ones of the second chip regions with the first wafer, and separating the bonded first and second wafers by a third dicing process.

Abstract: A coil component includes a body including a first surface and a second surface opposing each other and first to fourth side surfaces connecting the first and second surfaces; a first coil disposed within the body and including a first lead-out portion and a second lead-out portion extending to at least one of the first to fourth side surfaces of the body; a second coil disposed within the body and including a third lead-out portion and a fourth lead-out portion extending to at least one of the first to fourth side surfaces of the body; first to fourth external electrodes disposed on two adjacent side surfaces of the first to fourth side surfaces of the body and respectively connected to the first to fourth lead-out portions.

Abstract: Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1st fin structures on the substrate; and a plurality of multi-fin VFETs each of which includes a plurality of 2nd fin structures on the substrate, wherein a fin pitch of the 2nd fin structures is smaller than a fin pitch of the Pt fin structures.

Abstract: A capacitor component includes a body including a dielectric layer and first and second internal electrode layers, and external electrodes disposed on the body and connected to the first and second internal electrode layers, respectively. The body includes an active portion in which the first and second internal electrode layers are alternately disposed with the dielectric layer interposed therebetween, a cover portion disposed on an upper portion and a lower portion of the active portion, and a side margin portion disposed on both sides of the active portion opposing each other. When a content of magnesium (Mg) included in the active portion is A1, a content of magnesium (Mg) included in the cover portion is C1, and a content of magnesium (Mg) included in the margin portion is M1, 0<A1<M1?C1 and A1/C1?0.60 are satisfied.

Abstract: There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

Abstract: The present disclosure provides apparatuses including a capacitor structure. In some embodiments, an integrated circuit includes a substrate, and a capacitor structure, disposed above the substrate in a vertical direction, including a first electrode configured to receive a first voltage and including at least one first metal line having a first patterned side surface, a second electrode configured to receive a second voltage and including at least one second metal line having a second patterned side surface, and a dielectric layer disposed between the first electrode and the second electrode. The at least one first metal line and the at least one second metal line extend in a first horizontal direction. The first electrode, the second electrode, and the dielectric layer are disposed on a same layer. The at least one second metal line is spaced apart from the at least one first metal line in a second horizontal direction.

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, a heat dissipation layer on the first semiconductor chip and in contact with an upper surface of the first semiconductor chip, a second redistribution substrate on the heat dissipation layer, a molding layer surrounding the first semiconductor chip and the heat dissipation layer between the first redistribution substrate and the second redistribution substrate, through electrodes vertically penetrating the molding layer and electrically connecting the first redistribution substrate and the second redistribution substrate, the through electrodes being spaced apart from the first semiconductor chip and the heat dissipation layer, and dummy patterns vertically penetrating the molding layer and in contact with a side surface of the first semiconductor chip and a side surface of the heat dissipation layer.

Abstract: A display device includes: a display panel; a light emitting unit; a driving circuit configured to control a driving current applied to the light emitting unit based on image data; and a controller configured to: obtain a selected mode of one of a low grayscale mode or a high grayscale mode based on a required luminance included in the image data, obtain a minimum value and a maximum value of the driving current based on the selected mode, based on an output range of the driving current being adjusted to obtain an adjusted output range, increase a number of luminance levels expressible within the adjusted output range to obtain an increased number of luminance levels, and control the driving circuit based on the increased number of luminance levels.

Abstract: A coil component includes: a body; first and second support members disposed in the body; first and second coils disposed on the first support member; first and second vias connecting the first and second coils; third and fourth coils disposed on the second support member; and third and fourth vias connecting the third and fourth coils, wherein each innermost turn of the first and second coils has a parallel connection section between a point connected to the first via and a point connected to the second via, each innermost turn of the third and fourth coils has a parallel connection section between a point connected to the third via and a point connected to the fourth via, and a line width of each innermost turn of the first to fourth coils in the parallel connection section is smaller than a line width of each adjacent outer turn.

Abstract: A display panel includes a base layer including a first display region, a second display region adjacent to the first display region, and a non-display region adjacent to the first display region and the second display region, a demultiplexer circuit overlapping the second display region, a first pixel including a first pixel driver overlapping the first display region, and a first light emitting element overlapping the first display region and electrically connected with the first pixel driver, and a second pixel including a second pixel driver overlapping the first display region, and a second light emitting element and a third light emitting element that are electrically connected with the second pixel driver. At least one of the second light emitting element and the third light emitting element overlaps the second display region and is disposed on the demultiplexer circuit.

Abstract: A coil component includes: a body having a first and a second surface opposing each other, and a third and a fourth surface opposing each other and connecting the first surface and second surface; a support member disposed within the body; first and second coils disposed on the support member; first and third external electrodes disposed on the body and connected to the first coil; second and fourth external electrodes disposed on the body and connected to the second coil; a first via electrode disposed within the body and connecting the first coil and the first external electrode; and a second via electrode disposed within the body and connecting the second coil and the second external electrode, wherein the first to fourth external electrodes are disposed on the first surface, the third external electrode extends onto the third surface, and the fourth external electrode extends onto the fourth surface.

Abstract: A substrate bonding method includes: forming first plasma on a bonding surface of a first substrate at atmospheric pressure by using a mixed gas including an inert gas and water vapor, to thereby perform surface activation treatment on the bonding surface of the first substrate; forming second plasma on a bonding surface of a second substrate at atmospheric pressure by using the mixed gas, to thereby perform surface activation treatment on the bonding surface of the second substrate; bonding the bonding surface of the first substrate and the bonding surface of the second substrate to each other; and moving each of the first substrate and the second substrate at a constant speed in a region above a linear reactor in which the first plasma and the second plasma are formed.

Abstract: A multilayer capacitor includes a body including dielectric layers and internal electrodes and external electrodes disposed on an external surface of the body and connected to the internal electrodes. The body includes a first surface and a second surface to which the internal electrodes are exposed, the first surface and the second surface opposing each other in a first direction, a third surface and a fourth surface opposing each other in a second direction which is a direction in which the dielectric layers are stacked, and a fifth surface and a sixth surface opposing each other in a third direction. At least one of the internal electrodes include a first bottleneck structure having a first directional length of a third-directional outer region smaller than an inner region thereof and a second bottleneck structure having a third directional length of a first directional outer region smaller than an inner region thereof.

Abstract: A semiconductor package includes a redistribution structure, a semiconductor chip on the redistribution structure, a conductive filler between the redistribution structure and the semiconductor chip and connecting the redistribution structure to the semiconductor chip, and a support post between the redistribution structure and the semiconductor chip, the support post being spaced apart from the conductive filler, where the support post includes a first post on a top surface of the redistribution structure, and a second post including a first end connected to the first post and a second end oriented toward the semiconductor chip and supporting the semiconductor chip.

Abstract: A multilayer electronic component includes a body including a dielectric layer and an internal electrode, an external electrode disposed outside the body, and an insulating layer disposed on the external electrode. The external electrode is disposed to cover an exposed surface of an outermost surface of the electrode layer, and is formed to have a thickness, equal to or less than a thickness of the body, and the insulating layer is disposed to cover an end of the external electrode, to improve moisture resistance reliability.

Abstract: A semiconductor package is provided and includes: a first redistribution structure including a first redistribution pattern and a first redistribution insulating layer, wherein the first redistribution pattern includes a first redistribution via extending in a vertical direction within the first redistribution insulating layer; a second redistribution structure on the first redistribution structure and including a second redistribution pattern and a second redistribution insulating layer, wherein the second redistribution pattern includes a lower redistribution pad at a lower surface of the second redistribution insulating layer; a first semiconductor chip on the second redistribution structure; and a second semiconductor chip on the first semiconductor chip.

Abstract: Provided is a display apparatus that includes a display panel including a plurality of pixels; a driver configured to drive the plurality of pixels based on image data; a controller configured to provide the image data to the driver. The display apparatus is configured to identify a pixel that does not comprise the B light emitting device, from among the plurality of pixels, based on the position information stored in the memory; generate compensated image data for a B light emitting device in at least one adjacent pixel from among the plurality of pixels, that is adjacent with the identified pixel, and for a green (G) light emitting device in the identified pixel; and provide the compensated image data to the driver to display an image frame.

Abstract: A memory device includes a memory cell array including a plurality of memory cells coupled to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation based on a weighted access count on the memory cell array, a register configured to store a weighted access count for each of a plurality of row addresses; an accumulator configured to accumulate a current weighted access count corresponding to an access spacing to the weighted access count stored in the register, and a calculator configured to calculate the access spacing.

Abstract: A semiconductor package includes an interposer including a first redistribution layer and a second redistribution layer that is on the first redistribution layer and is electrically coupled to the first redistribution layer; and a semiconductor chip on the interposer. The first redistribution layer includes a first organic insulating layer and a plurality of first conductors in the first organic insulating layer. The second redistribution layer includes a second organic insulating layer, a first silicon insulating layer on the second organic insulating layer, and a plurality of second conductors penetrating through both the second organic insulating layer and the first silicon insulating layer. The semiconductor chip includes a second silicon insulating layer and a plurality of third conductors in the second silicon insulating layer.

Abstract: A memory device includes a multi-phase clock generator configured to generate first to N-th clock signals having N different phases based on a clock signal from the memory controller, and a monitoring clock signal generator configured to generate a monitoring clock signal having a logic state corresponding to a data pattern in synchronization with edges of the first to N-th clock signals, wherein the monitoring clock signal includes a first monitoring clock signal configured to detect a skew between the first and third clock signals in a first step of a training operation, a second monitoring clock signal configured to detect a skew between the second and fourth clock signals in a second step of the training operation, and a third monitoring clock signal configured to detect a skew between the first and second clock signals in a third step of the training operation.

Abstract: A semiconductor device includes a substrate having first and second regions; a first stack structure including lower gate electrodes stacked in a first direction in the first region; a first channel structure penetrating through the first stack structure; a second stack structure on the first stack structure and the first channel structure and including upper gate electrodes stacked in the first direction; a second channel structure penetrating through the second stack structure; a first mold structure including lower horizontal sacrificial layers stacked in the second region; an alignment structure penetrating through the first mold structure; and a second mold structure on the first mold structure and the alignment structure and including upper horizontal sacrificial layers stacked, wherein the number of the lower horizontal sacrificial layers is less than the number of the lower gate electrodes.

Abstract: Provided are memory devices and memory systems. The memory device includes a memory cell array in a first semiconductor layer and including word lines stacked in a first direction, and channel structures passing through the word lines in the first direction; a control logic circuit in a second semiconductor layer located below the first semiconductor layer in the first direction; and a physical unclonable function (PUF) circuit including a plurality of through electrodes passing through the first semiconductor layer and the second semiconductor layer, and configured to generate PUF data according to resistance values of the plurality of through electrodes, and generate the PUF data based on a node voltage between through electrodes connected in series, among the plurality of through electrodes.

Abstract: Disclosed is a memory device which a memory cell array including a plurality of memory blocks, a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block from among the plurality of memory blocks, in which an erase operation is to be performed, and control logic configured to control the memory cell array and the voltage generator. The voltage generator is configured to provide the erase voltage to at least one of a bit line and a common source line connected with the target block and to provide the row line voltages to row lines connected with the target block, and the control logic is configured to change a slope of the erase voltage and a floating time of at least one row line among the row lines depending on a program/erase cycle.