Abstract: A device includes a heterojunction device, a unipolar power transistor operatively connected in series with said hetero junction device; an external control terminal for driving said unipolar power transistor and said heterojunction device; and an interface unit having a plurality of interface terminals. A first interface terminal is operatively connected to an active gate region of the heterojunction device and a second interface terminal is operatively connected to said external control terminal. The heterojunction device includes a threshold voltage less than a threshold voltage of the unipolar power transistor, wherein the threshold voltage of the heterojunction device is less than a blocking voltage of the unipolar power transistor.

Abstract: Disclosed herein is a light emitting device and method of manufacturing such a device comprised of a series of photopolymerizable, chiral liquid crystalline layers that can be solvent cast on a substrate. The mixture of chiral materials in each successive layer may be blended in such a way that each layer has the same chiral pitch. Further the chiral materials in each layer may also be blended so that the ordinary and extraordinary refractive indices in each layer match the other layers such that the complete assembly of layers will optically function as a single relatively thick layer of chiral liquid crystal. The chiral nematic material in each layer can spontaneously adopt a helical structure with a helical pitch. The light emitting layers of the light emitting device can further comprise electroluminescent material that emits light into the band edge light propagation modes of the photonic crystal.

Abstract: According to one embodiment, a semiconductor memory device includes a mounting board and memory dies. The memory dies include first pad electrodes, first pull-up circuits connected to the first pad electrodes, a first output circuit that outputs a first parameter to the first pull-up circuits, first pull-down circuits connected to the first pad electrodes, a second output circuit that outputs a second parameter to the first pull-down circuits, a second pad electrode, a second pull-up circuit connected to the second pad electrode, a third output circuit that is connected to the second pad electrode, a third pad electrode, a second pull-down circuit connected to the third pad electrode, and a fourth output circuit that is connected to the third pad electrode. The second pad electrode of the second memory die is connected to the third pad electrode of the first memory die.

Abstract: An integrated circuit (IC) package comprising a substrate having a dielectric, a first structure over at least a portion of the dielectric, the first structure comprising a molecular compound having a ligand coordinating moiety and a second structure over at least a portion of the first structure, the second structure comprising a metal, wherein the first structure is chemically bonded to the dielectric.

Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices using epitaxially grown piezoelectric films. In some cases, the piezoelectric layer of the FBAR may be an epitaxial III-V layer such as an aluminum nitride (AlN) or other group III material-nitride (III-N) compound film grown as a part of a III-V material stack, although any other suitable piezoelectric materials can be used. Use of an epitaxial piezoelectric layer in an FBAR device provides numerous benefits, such as being able to achieve films that are thinner and higher quality compared to sputtered films, for example. The higher quality piezoelectric film results in higher piezoelectric coupling coefficients, which leads to higher Q-factor of RF filters including such FBAR devices. Therefore, the FBAR devices can be included in RF filters to enable filtering high frequencies of greater than 3 GHz, which can be used for 5G wireless standards, for example.

Abstract: Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

Abstract: An electronic product that includes a component having a first electrode with a first surface and a pillar extending from the first surface in a first direction, the pillar having three protrusions, the three protrusions forming angles of about 120 degrees with each other around a central line of the pillar where the three protrusions meet, and the three protrusions being bent so that the pillar has a triskelion cross-section in a plane perpendicular to the first direction.

Abstract: Fabrication of vertical diodes for radiation sensing using a low temperature microwave anneal is provided. This kind of anneal allows the back side processing to be performed after the front side processing is done without damaging the front side structures. This enables a simplified fabrication of thinned detectors compared to a conventional silicon on insulator process. Another feature that this technology enables is a thin entrance window for a detector that also serves as the doped diode termination. Such thin entrance windows are especially suitable for detection of low energy radiation.

Abstract: According to an aspect, an image sensor package includes a transparent member, a substrate, and an interposer disposed between and coupled to the transparent member and the substrate, where the interposer defines a first cavity area and a second cavity area. The image sensor package includes an image sensor die disposed within the first cavity area of the interposer, where the image sensor die has a sensor array configured to receive light through the transparent member and the second cavity area. The image sensor package includes a bonding material that couples the image sensor die to the interposer within the first cavity area.

Abstract: A chemical mechanical polishing system includes a metrology station having a sensor configured to measure a thickness profile of a substrate, a robotic arm configured to transfer the substrate from the metrology station to a polishing station having, a platen to support a polishing pad having a polishing surface, a carrier head on the polishing surface, the carrier head having a membrane configured to apply pressure to the substrate in the carrier head, and a controller configured to receive measurements from the sensor and configured to control the robotic arm to orient the substrate in the carrier head according to substrate profile and a removal profile for the carrier head.

Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate and forming a second insulating film on the first insulating film. The first insulating film is a tensile film having a first tensile stress and the second insulating film is either a tensile film having a second tensile stress that is less than the first tensile stress or a compressive film. The first insulating film and second insulating film are formed of a same material. A metal hard mask layer is formed on the second insulating film.

Abstract: A package structure includes at least one electronic device, a protection layer and an encapsulant. The electronic device has a first surface and includes a plurality of bumps disposed adjacent to the first surface thereof. Each of the bumps has a first surface. The protection layer covers the bumps and the first surface of the electronic device, and has a first surface. The encapsulant covers the protection layer and at least a portion of the electronic device, and has a first surface. The first surfaces of the bumps, the first surface of the protection layer and the first surface of the encapsulant are substantially coplanar with each other.

Abstract: A circuit carrier for holding at least one electrical power component is disclosed. The circuit carrier including a heat sink for holding and for cooling the power component. The heat sink having a surface. The circuit carrier includes a copper layer for mechanically connecting the heat sink to at least one copper plate, where the copper layer includes copper or a copper alloy and is cold-gas-sprayed or sintered on the surface of the heat sink. The circuit carrier also includes at least one copper plate for mechanically and electrically connecting the power component to the copper layer. The copper plate includes copper or a copper alloy and is arranged directly on a surface of the copper layer facing away from the heat sink and is areally, mechanically and electrically conductively connected to the copper layer.

Abstract: A substrate for RF devices includes a polycrystalline ceramic core and an interlayer structure. The interlayer structure includes a first silicon oxide layer coupled to the polycrystalline ceramic core, a polysilicon layer coupled to the first silicon oxide layer, a second silicon oxide layer coupled to the polysilicon layer, a barrier layer coupled to the second silicon oxide layer, a third silicon oxide layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the third silicon oxide layer.

Abstract: The present invention ultra-low loss high energy density dielectric layers having femtosecond (10?15 sec) polarization response times within a chip stack assembly to extend impedance-matched electrical lengths and mitigate ringing within the chip stack to bring the operational clock speed of the stacked system closer to the intrinsic clock speed(s) of the semiconductor die bonded within chip stack.

Abstract: The disclosure relates to a III-nitride power semiconductor based heterojunction device including a low voltage terminal, a high voltage terminal, a control terminal and an active heterojunction transistor formed on a substrate, and further including the following monolithically integrated components: voltage clamp circuit configured to limit a maximum potential that can be applied to the internal gate terminal, an on-state circuit configured to control the internal gate terminal of the active heterojunction transistor during an on-state operation, a turn-off circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-off operation and during an off-state.

Abstract: Pastes are disclosed that are configured to coat a passage of a substrate. When the paste is sintered, the paste becomes electrically conductive so as to transmit electrical signals from a first end of the passage to a second end of the passage that is opposite the first end of the passage. The metallized paste contains a lead-free glass frit, and has a coefficient of thermal expansion sufficiently matched to the substrate so as to avoid cracking of the sintered paste, the substrate, or both, during sintering.

Abstract: A display apparatus includes a substrate in which a plurality of pads are disposed, a plurality of micro LEDs, wherein each micro LED from among the plurality of micro LEDs is electrically connected to a respective group of pads from among the plurality of pads and mounted on the substrate, and a plurality of protrusion members, wherein each protrusion member from among the plurality of protrusion members protrudes from the substrate and is formed adjacent to a respective pad from among the plurality of pads.

Abstract: A semiconductor device including a first conductivity type substrate, a first conductivity type carrier store layer formed on an upper surface side of the substrate, a second conductivity type channel dope layer formed on the carrier store layer, a first conductivity type emitter layer formed on the channel dope layer, a gate electrode in contact with the emitter layer, the channel dope layer and the carrier store layer via a gate insulating film, and a second conductivity type collector layer formed on a lower surface side of the substrate, wherein the gate insulating film has a first part in contact with the emitter layer and the channel dope layer, a second part in contact with the carrier store layer, and a third part in contact with the substrate, and at least a part of the second part is thicker than the first part and the third part.

Abstract: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section.