Abstract: A thin film transistor, a method for fabricating the same, a display substrate, and a display device are disclosed. The thin film transistor includes a gate, a source, a drain, and an active layer. Forming the active layer includes: forming a pattern comprising a thermal insulation layer; forming a pattern comprising an amorphous silicon layer on the thermal insulation layer, wherein the pattern comprising the amorphous silicon layer includes a first portion on the thermal insulation layer and a second portion extending beyond the thermal insulation layer; and treating the pattern comprising the amorphous silicon layer with a laser annealing process, so that the amorphous silicon layer grows grain in a direction from the second portion to the first portion to form the active layer from polycrystalline silicon.

Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a substrate, a first conductive layer disposed on the substrate, a patterned oxide layer disposed on the first conductive layer and the substrate, exposing a part of the first conductive layer, a second conductive layer disposed on the exposed first conductive layer and the patterned oxide layer, an antiferroelectric layer disposed on the exposed first conductive layer and the second conductive layer, a ferroelectric layer disposed on the second conductive layer and located on the antiferroelectric layer, a conductive oxide layer disposed between the antiferroelectric layer, and a third conductive layer disposed on the conductive oxide layer and between the ferroelectric layer.

Abstract: A semicondcutor memory device may include a substrate, a bit line structure extending in one direction on the substrate, the bit line structure including a sidewall, a storage node contact on the sidewall of the bit line structure, first and second spacers between the sidewall of the bit line structure and the storage node contact, the first spacer separated from the second spacer by a space between the first spacer and the second spacer, an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface, a spacer capping pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first and second spacers, and a landing pad structure penetrating the interlayer dielectric layer, the landing pad structure coupled to the storage node contact.

Abstract: A method of forming an integrated circuit includes forming a first layer having a first material type over a first side of a semiconductor wafer. A second layer having a second different material type is removed from a second opposing side of the semiconductor wafer using a first process that removes the second material type at a greater rate than the first material type. Subsequent to removing the second layer, the first layer is removed using a second different process.

Abstract: An IC assembly including an exposed pad integrated circuit (“IC”) package having a thermal pad with a top surface and a bottom surface and with at least one peripheral surface portion extending transversely of and continuous with the bottom surface. The bottom surface and the at least one peripheral surface are exposed through a layer of mold compound. Also, methods of making an exposed pad integrated circuit (“IC”) package assembly. One method includes optically inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. Another method includes wave soldering an exposed pad of an IC package to a printed circuit board.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements and forming a metal gate stack in the recess. The method further includes etching back the metal gate stack while the metal gate stack is kept at a temperature that is in a range from about 20 degrees C. to about 55 degrees C. In addition, the method includes forming a protection element over the metal gate stack after etching back the metal gate stack.

Abstract: Provided is a thin film transistor including a source electrode, a drain electrode, and a channel layer connecting the source electrode and the drain electrode. The channel layer includes a tin-based oxide represented by SnMO, wherein M includes at least one of a non-metal chalcogen element or a halogen element.

Abstract: A composition for use as an electronic material. The composition contains at least one organic semiconducting material, and at least one electrically insulating polymer forming a semiconducting blend wherein the insulating polymer acts as a matrix for the organic semiconducting material resulting in an interpenetrating morphology of the polymer and the semiconductor material. The variation of charge carrier mobility with temperature in the semiconducting blend is less than 20 percent in a temperature range. A method of making a film of an electronic material. The method includes dissolving at least one organic semiconducting material and at least one insulating polymer into an organic solvent in a pre-determined ratio resulting in a semiconducting blend, depositing the blend onto a substrate to form a film comprising an interpenetrating morphology of the at least one insulating polymer and the at least one organic semiconductor material.

Abstract: The present invention provides an organic electroluminescence device having excellent luminous efficiency and excellent luminance. The present invention relates to an organic electroluminescence device including a structure in which a plurality of layers is laminated between an anode and a cathode formed on a substrate; wherein the organic electroluminescence device includes a metal oxide layer between the anode and the cathode; and a nitrogen-containing film layer having an average thickness of not less than 0.1 nm but less than 3 nm adjacent to the metal oxide layer and disposed on an anode side.

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells are in the stack. The channel-material strings project upwardly from material of an uppermost of the tiers. A first insulator material is above the material of the uppermost tier directly against sides of channel material of the upwardly-projecting channel-material strings. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is above the first insulator material. The first and second insulator materials comprise different compositions relative one another. Conductive vias in the second insulator material are individually directly electrically coupled to individual of the channel-material strings. Other embodiments, including methods, are disclosed.

Abstract: A strip for an electronic device senses a liquid sample. The strip includes a substrate having a first surface, a plurality of protrusions disposed on the first surface, and each having a width, and a hydrophilic layer having a layer surface disposed on the first surface and the plurality of protrusions, and having a second surface opposite to the layer surface, whereby the liquid sample and the second surface have a contact angle therebetween ranging from 2 to 85 degrees when the liquid sample is disposed on the hydrophilic layer.

Abstract: Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.

Abstract: An optical sensor package module and a manufacturing method thereof are provided. The optical sensor package module includes a substrate, a sensor chip and a shielding assembly. The sensor chip is disposed on the substrate and includes an array of pixels located at a top side thereof for receiving light. The shielding assembly surrounds the sensor chip for limiting influx of light onto the sensor chip, and the shielding assembly includes a frame and a shielding element. The shielding element has a first light-permeable region disposed above at least a first subset of the pixels, the first subset is configured to receive corresponding light, and the first light-permeable region is transparent to the corresponding light. The shielding element includes an engaging structure formed thereon, and the shielding element is engaged with the frame by the engaging structure.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions.

Abstract: A metal capacitor provided includes a first metal layer and a second metal layer disposed above a substrate. The first metal layer includes a first electrode sheet and a second electrode sheet, and the second metal layer includes a third electrode sheet and a fourth electrode sheet. The first electrode sheet and the second electrode sheet collectively form a first coplanar capacitor. The third electrode sheet and the fourth electrode sheet collectively form a second coplanar capacitor. At least a portion of the fourth electrode sheet is arranged above the first electrode sheet, and the first electrode sheet and the fourth electrode sheet collectively form a first vertical capacitor. At least a portion of the third electrode sheet is arranged above the second electrode sheet, and the second electrode sheet and the third electrode sheet collectively form a second vertical capacitor.

Abstract: A substrate processing method is described for forming a titanium nitride material that may be used for superconducting metallization or work function adjustment applications. The substrate processing method includes depositing by vapor phase deposition at least one monolayer of a first titanium nitride film on a substrate, and treating the first titanium nitride film with plasma excited hydrogen-containing gas, where the first titanium nitride film is polycrystalline and the treating increases the (200) crystallographic texture of the first titanium nitride film. The method further includes depositing by vapor phase deposition at least one monolayer of a second titanium nitride film on the treated at least one monolayer of the first titanium nitride film, and treating the at least one monolayer of the second titanium nitride film with plasma excited hydrogen-containing gas.

Abstract: An interconnect structure and methods of forming the interconnect structure an interconnect dielectric including at least one contact landing within the interconnect dielectric and/or underlying the interconnect dielectric. The structure and methods include roughening an exposed surface of at least one contact landing to increase the surface area of a conductive metal subsequently disposed in a contact feature and in direct contact with the roughened surface of the least one contact landing.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.

Abstract: A method includes bonding a device die to an interposer. The interposer includes a through-via extending from a top surface of a semiconductor substrate of the interposer into an intermediate level between the top surface and a bottom surface of the semiconductor substrate. A singulation process is performed to saw the interposer and the device die into a package. The method further includes placing the package over a carrier, encapsulating the package in an encapsulant, thinning the encapsulant and the semiconductor substrate of the interposer until the through-via is exposed, and forming redistribution lines, wherein a redistribution line in the redistribution lines is in contact with the through-via.

Abstract: A substrate for RF devices includes a polycrystalline ceramic core and an interlayer structure. The interlayer structure includes a first silicon oxide layer coupled to the polycrystalline ceramic core, a polysilicon layer coupled to the first silicon oxide layer, a second silicon oxide layer coupled to the polysilicon layer, a barrier layer coupled to the second silicon oxide layer, a third silicon oxide layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the third silicon oxide layer.