Abstract: A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound.

Abstract: Present example embodiments relate generally to methods of fabricating a three-dimensional gate-all-around (GAA) vertical gate (VG) semiconductor structure comprising providing a substrate; forming a plurality of layers having alternating first insulative material layers and second insulative material layers over the substrate; identifying bit line and word line locations for the formation of bit lines and word lines; removing at least a portion of the plurality of layers outside of the identified bit line and word line locations, each of the removed portions extending through the plurality of layers to at least a top surface of the substrate; forming a vertical first insulative material structure in the removed portions; performing an isotropic etching process to remove the second insulative material from the second insulative material layers; forming bit lines in the second insulative material layers within the identified bit line locations; and forming word lines in the identified word line locations.

Abstract: A structure and method for reducing second-order harmonic distortion in FET devices used in applications that are sensitive to such distortion, such as switching RF signals. The asymmetry of the drain-to-body capacitance Cdb and source-to-body capacitance Csb of a FET device are equalized by adding offsetting capacitance or a compensating voltage source.

Abstract: Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.

Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

Abstract: A system has a leadframe with leads and a pad. The pad surface having a portion recessed with a depth and an outline suitable for attaching a semiconductor chip. A first chip is vertically stacked to the opposite pad surface. A clip is vertically stacked on the first chip and tied to a lead. A second chip has a terminal attached to the recessed portion and terminals co-planar with the un-recessed portion. A second chip is attached to the clip.

Abstract: Provided is an organic light-emitting display apparatus including a substrate; and a plurality of pixels on the substrate, wherein each of the pixels comprise: an organic light-emitting device comprising a first electrode, a second electrode, and an intermediate layer between the first electrode and the second electrode, wherein the intermediate layer comprises an organic emission layer; a driving transistor configured to drive the organic light-emitting device; and a switching transistor electrically coupled to the driving transistor, wherein the gate electrode of the driving transistor comprises a first conductive layer, and a second conductive layer between the first conductive layer and the active layer of the driving transistor and has a smaller size than the first conductive layer, and the gate electrode of the switching transistor comprises a same material as the first conductive layer.

Abstract: A semiconductor device includes a semiconductor region, a first electrode provided on the semiconductor region, a second electrode provided on the semiconductor region adjacent to and spaced from a side of the first electrode, and containing an identical material as the material of the first electrode, a third electrode provided on the semiconductor region in a location between the first electrode and the second electrode, a first insulating film provided between the semiconductor region and the third electrode, and a fourth electrode connected to the third electrode containing the same material as the material of the first electrode and the second electrode.

Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.

Abstract: An oxide semiconductor layer with excellent crystallinity is formed to enable manufacture of transistors with excellent electrical characteristics for practical application of a large display device, a high-performance semiconductor device, etc. By first heat treatment, a first oxide semiconductor layer is crystallized. A second oxide semiconductor layer is formed over the first oxide semiconductor layer. By second heat treatment, an oxide semiconductor layer including a crystal region having the c-axis oriented substantially perpendicular to a surface is efficiently formed and oxygen vacancies are efficiently filled. An oxide insulating layer is formed over and in contact with the oxide semiconductor layer. By third heat treatment, oxygen is supplied again to the oxide semiconductor layer. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer.

Abstract: The present invention relates to a method for manufacturing an epitactic silicon layer made up of crystallites with a size no lower than 20 ?m, including: providing a layer of crystallized silicon the surface of which, being inhomogeneous in terms of the size of the crystallites, is made up of large crystallites with a size no lower than 20 ?m, and small crystallites of a smaller size; forming, on the surface of the inhomogeneous silicon layer, a layer of at least one non-nucleating material for the silicon, the thickness of which is adjusted such to cover the entire outer surface of the small crystallites, while leaving all or part of the outer surface of the large crystallites accessible; and carrying out epitaxial growth of a silicon layer on the surface of the assembly obtained at the end of step, under conditions that are suitable for forming the expected epitactic layer.

Abstract: One device disclosed includes a gate structure positioned around a perimeter surface of the fin, a layer of channel semiconductor material having an axial length in the channel length direction of the device that corresponds approximately to the overall width of the gate structure being positioned between the gate structure and around the outer perimeter surface of the fin, wherein an inner surface of the layer of channel semiconductor material is spaced apart from and does not contact the outer perimeter surface of the fin. One method disclosed involves, among other things, forming first and second layers of semiconductor material around the fin, forming a gate structure around the second semiconductor material, removing the portions of the first and second layers of semiconductor material positioned laterally outside of sidewall spacers and removing the first layer of semiconductor material positioned below the second layer of semiconductor material.

Abstract: An organic light emitting display device includes a thin film transistor on a substrate, a first protection layer covering the thin film transistor, a conductive organic layer on the first protection layer and coupled to the thin film transistor, and an organic light emitting device on the conductive organic layer and coupled to the conductive organic layer.

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract: A semiconductor device includes an epitaxial layer including a first surface and a silicon layer disposed on the first surface and including a second surface opposite to the first surface, wherein the silicon layer includes a plurality of pillars on the second surface, a portion of the plurality of pillars on a predetermined portion of the second surface are in substantially same dimension, each of the plurality of pillars on the predetermined portion of the second surface stands substantially orthogonal to the second surface, the plurality of pillars are configured for absorbing an electromagnetic radiation of a predetermined wavelength projected from the epitaxial layer and generating an electrical energy in response to the absorption of the electromagnetic radiation.

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

Abstract: In a method of manufacturing a semiconductor device, which uses a triple patterning process, a porous layer covering sidewalls and an upper surface of a polymer-containing pattern is formed on a layer to be etched. A decomposition gas is supplied to the polymer-containing pattern through the porous layer, and a portion of the polymer-containing pattern is decomposed to form a reduced polymer-containing pattern and form a void between the reduced polymer-containing pattern and the porous layer. A portion of the porous layer is removed to form a porous spacer pattern spaced apart from the reduced polymer-containing pattern. The layer to be etched is etched by using the reduced polymer-containing pattern and the porous spacer pattern as an etch mask.

Abstract: A method for forming a stacked metal contact in electrical communication with aluminum wiring in a semiconductor wafer of an integrated circuit is disclosed. The method includes the steps of: forming at least one passivation layer on a surface of the semiconductor wafer of the integrated circuit, where an aluminum wiring is embedded; forming a patterned terminal via opening through the passivation layer to expose the aluminum wiring; removing a portion of the aluminum wiring from the patterned terminal via opening by chemical etching and forming a thin zinc film on an etched surface at the same time; forming a nickel film stacked on the zinc film; and; and forming a metal stack in the patterned terminal via opening and/or at least a portion of the passivation layer by chemical plating or metal plating.

Abstract: In one embodiment, a semiconductor device includes a first metal line disposed in a first metal level above a substrate. A second metal line is disposed in a second metal level disposed over the first metal level. A third metal line is disposed in a third metal level disposed over the second metal level. A through level via contacts the first metal line and the third metal line.

Abstract: Methods of modifying a self-aligned contact process in a semiconductor fabrication and a semiconductor device are provided. A method includes forming a transistor over a substrate, including depositing a high-k dielectric layer over the substrate; depositing a work function metal layer over the high-k dielectric layer; forming a metal gate over the work function metal layer; forming two spacers sandwiching the work function metal layer and the metal gate; and forming a doped region in the substrate; etching the work function metal layer and the metal gate to leave a metal residue over inner walls of the two spacers exposing the work function metal layer and the metal gate; modifying the metal residue and the exposed work function metal layer and metal gate to form a metal compound; depositing an insulator covering the metal compound; and forming contact pads respectively electrically connected to the metal gate and the doped region.