Patents Examined by Aaron A Dehne
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Patent number: 9105728Abstract: This disclosure provides implementations of multi-gate transistors, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes a thin-film semiconducting layer arranged over a substrate. A drain and source are coupled to the semiconducting layer. The device also includes first, second and third gates all arranged adjacent the semiconducting layer and configured to receive first, second, and third control signals, respectively. Dielectric layers insulate the gates from the semiconducting layer and from one another. In a first mode, the first, second, and third gates are configured such that charge is stored in a potential well in a region of the semiconducting layer adjacent the second gate. In a second mode, the first, second and third gate electrodes are configured such that the stored charge is transferred through the region of the semiconducting layer adjacent the third gate electrode and through the source to a load.Type: GrantFiled: July 24, 2012Date of Patent: August 11, 2015Assignee: QUALCOMM MEMS Technologies, Inc.Inventors: John Hyunchul Hong, Cheonhong Kim, Tze-Ching Fung
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Patent number: 9105665Abstract: Methods of forming memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.Type: GrantFiled: May 29, 2014Date of Patent: August 11, 2015Assignee: Micron Technology, Inc.Inventors: Rhett T. Brewer, Durai V. Ramaswamy
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Patent number: 9099489Abstract: A higher breakdown voltage transistor has separated emitter, base contact, and collector contact. Underlying the emitter and the base contact are, respectively, first and second base portions of a first conductivity type. Underlying and coupled to the collector contact is a collector region of a second, opposite, conductivity type, having a central portion extending laterally toward, underneath, or beyond the base contact and separated therefrom by the second base portion. A floating collector region of the same conductivity type as the collector region underlies and is separated from the emitter by the first base portion. The collector and floating collector regions are separated by a part of the semiconductor (SC) region in which the base is formed. A further part of the SC region in which the base is formed, laterally bounds or encloses the collector region.Type: GrantFiled: July 10, 2012Date of Patent: August 4, 2015Assignee: FREESCALE SEMICONDUCTOR INC.Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
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Patent number: 9099401Abstract: Semiconductor devices include a first and a second set of parallel fins, each set of fins having a same number of fins and a pitch between adjacent fins below a minimum pitch of an associated lithography process, where a spacing between the first and second set of fins is greater than the pitch between adjacent fins; a gate structure over the first and second sets of fins; a merged source region that connects the first and second sets of fins on a first side of the gate structure; and a merged drain region that connects the first and second sets of fins on a second side of the gate structure.Type: GrantFiled: September 17, 2013Date of Patent: August 4, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
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Patent number: 9064885Abstract: A diode and a method for an electrostatic discharge resistant diode. The method includes, for example, receiving a wafer. The wafer includes a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. An N-type well is implanted in the silicon substrate. Furthermore, a vertical column of P+ doped epitaxial silicon and a vertical column of N+ doped epitaxial silicon are formed over the N-type well and extend through the BOX layer and the silicon layer. Both vertical columns may form electrical junctions with the N-type well.Type: GrantFiled: September 25, 2013Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: Huiming Bu, Robert J. Gauthier, Jr., Terence B. Hook, Effendi Leobandung, Tenko Yamashita
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Patent number: 9054226Abstract: A semiconductor device includes a plurality of lower electrodes on a substrate, with each of the lower electrodes extending in a height direction from the substrate and including sidewalls, the lower electrodes being spaced apart from each other in a first direction and in a second direction, a plurality of first supporting layer patterns contacting the sidewalls of the lower electrodes, the first supporting layer patterns extending in the first direction between ones of the lower electrodes adjacent in the second direction, a plurality of second supporting layer patterns contacting the sidewalls of the lower electrodes, the second supporting layer pattern extending in the second direction between ones of the lower electrodes adjacent in the first direction, the plurality of second supporting layer patterns being spaced apart from the plurality of first supporting layer patterns in the height direction.Type: GrantFiled: July 11, 2012Date of Patent: June 9, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Ho Lee, Jin Choi, Yong-Ho Yoo, Jong-Hyuk Kang, Hyun-Joo Cha, Hee-Dong Park, Tae-Jung Park
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Patent number: 9054124Abstract: A diode and a method for an electrostatic discharge resistant diode. The method includes, for example, receiving a wafer. The wafer includes a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. An N-type well is implanted in the silicon substrate. Furthermore, a vertical column of P+ doped epitaxial silicon and a vertical column of N+ doped epitaxial silicon are formed over the N-type well and extend through the BOX layer and the silicon layer. Both vertical columns may form electrical junctions with the N-type well.Type: GrantFiled: December 14, 2012Date of Patent: June 9, 2015Assignee: International Business Machines CorporationInventors: Huiming Bu, Robert J. Gauthier, Jr., Terence B. Hook, Effendi Leobandung, Tenko Yamashita
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Patent number: 9054215Abstract: Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.Type: GrantFiled: December 18, 2012Date of Patent: June 9, 2015Assignee: Intel CorporationInventors: Paul A. Nyhus, Swaminathan Sivakumar
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Metal-semiconductor convergence electric circuit devices and electric circuit systems using the same
Patent number: 9035427Abstract: Provided are metal-semiconductor convergence electric circuit devices. The device includes a semiconductor device, a metal resistor exhibiting resistance increased with an increase in temperature thereof, and an interconnection line connecting the semiconductor device with the metal resistor in series and having a resistance lower than that of the metal resistor. The semiconductor device is configured to exhibit resistance decreased with an increase in temperature thereof and compensate the resistance increase of the metal resistor.Type: GrantFiled: July 1, 2011Date of Patent: May 19, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyun-Tak Kim, Bongjun Kim -
Patent number: 9034769Abstract: A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.Type: GrantFiled: December 12, 2012Date of Patent: May 19, 2015Assignee: Micron Technology, Inc.Inventors: Mark A. Bossler, Jaspreet S. Gandhi, Christopher J. Gambee, Randall S. Parker
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Patent number: 9023664Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.Type: GrantFiled: February 26, 2013Date of Patent: May 5, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi-Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo-Fei Wang, Ming-Yu Fan, Jong-I Mou
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Patent number: 9024300Abstract: An apparatus including: a stacked structure including a first substrate having a flat surface; a flat first graphene layer adjacent the flat surface of the first substrate; a flat second graphene layer adjacent the flat first graphene layer; and a second substrate having a flat surface adjacent the flat second graphene layer. An apparatus including: a stacked structure including a substrate having a flat upper surface; a flat lower patterned layer overlying the flat upper surface of the substrate and including at least one patterned electrode; a flat lower graphene layer overlying the flat lower patterned layer; a flat upper graphene layer overlying the flat lower graphene layer; and a flat upper patterned layer overlying the flat upper graphene layer and including at least one patterned electrode.Type: GrantFiled: May 13, 2010Date of Patent: May 5, 2015Assignee: Nokia CorporationInventors: Martti Kalevi Voutilainen, Pirjo Pasanen
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Patent number: 9012926Abstract: A radiation-emitting semiconductor component includes a light-emitting diode chip with at least two emission regions that can be operated independently of each other and at least two differently designed conversion elements. During operation of the light-emitting diode chips each of the emission regions is provided for generating electromagnetic primary radiation. Each emission region has an emission surface by which at least part of the primary radiation is decoupled from the light-emitting diode chip. The conversion elements are provided for absorbing at least part of the primary radiation and for re-emitting secondary radiation. The differently designed conversion elements are disposed downstream of different emission surfaces. An electric resistance element is connected in series or parallel to at least one of the emission regions.Type: GrantFiled: August 5, 2010Date of Patent: April 21, 2015Assignee: Osram Opto Semiconductor GmbHInventors: Norwin von Malm, Ralph Wirth
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Patent number: 8969855Abstract: An organic light emitting device includes, a base part, patterned first electrodes on the base part, conductive material layers spaced apart from the patterned first electrodes and between the first electrodes, pixel defining layers between the patterned first electrodes, the pixel defining layers overlapping only a portion of upper surfaces of the conductive material layers, light emitting layers on the first electrodes, and a second electrode on the light emitting layers.Type: GrantFiled: April 18, 2012Date of Patent: March 3, 2015Assignee: Samsung Display Co., Ltd.Inventor: Won-Kyu Kwak
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Patent number: 8969192Abstract: A bumped substrate is optimized to be flat post reflow. By producing the bumped substrate to be flat post reflow, device reliability is assured. More particularly, the transistor shift associated with warped substrates is avoided. Further, by producing a flat bumped substrate post reflow, reliability in the flip chip interconnections is assured as compared to the undesirable open circuits associated with warped substrates.Type: GrantFiled: October 27, 2010Date of Patent: March 3, 2015Assignee: Amkor Technology, Inc.Inventor: Robert Lanzone
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Patent number: 8969140Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.Type: GrantFiled: August 14, 2013Date of Patent: March 3, 2015Assignee: Intel CorporationInventors: Robert L. Sankman, John S. Guzek
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Patent number: 8963127Abstract: A white organic light emitting device having a dual stack structure is disclosed, in which an electron transport layer adjacent to a blue light emitting layer includes an electron transport catalyst layer including metal to improve blue light emitting efficiency, and a greenish yellow dopant is used to improve white display efficiency, increase lifespan, and reduce power consumption.Type: GrantFiled: October 22, 2010Date of Patent: February 24, 2015Assignee: LG Display Co., Ltd.Inventors: Sung-Hoon Pieh, Chang-Oh Kim
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Patent number: 8951843Abstract: The present invention provides a laminated sheet that can prevent the decrease in adhering strength of a resin composition layer and the deterioration in electrical reliability and in which a back grinding tape can be peeled from a plurality of semiconductor elements collectively after dicing. The laminated sheet has a back grinding tape in which a pressure-sensitive adhesive layer is formed on a base, and a resin composition layer that is provided on the pressure-sensitive adhesive layer of the back grinding tape, wherein the tensile modulus of the pressure-sensitive adhesive layer at 23° C. is 0.1 to 5.0 MPa, and the T-peeling strength between the pressure-sensitive adhesive layer and the resin composition layer is 0.1 to 5 N/20 mm at 23° C. and 300 mm/min.Type: GrantFiled: December 12, 2012Date of Patent: February 10, 2015Assignee: Nitto Denko CorporationInventors: Hiroyuki Senzai, Shumpei Tanaka, Koji Mizuno
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Patent number: 8951888Abstract: A method for fabricating a semiconductor device includes a first step of forming, on a first substrate, a first element region in which a plurality of elements are collectively arranged, a second step of relocating the plurality of elements formed on the first substrate to a holding member in the same arrangement as in the first element region to have the plurality of elements held on the holding member, a third step of rearranging the plurality of elements held on the holding member and having the plurality of elements held on an intermediate substrate, thereby forming a second element region having a shape different from a shape of the first element region on the intermediate substrate, and a fourth step of dispersing the plurality of elements held on the intermediate substrate and adhering the plurality of elements to a second substrate.Type: GrantFiled: May 23, 2011Date of Patent: February 10, 2015Assignee: Sharp Kabushiki KaishaInventor: Katsuyuki Suga
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Patent number: 8951809Abstract: A method of carrying out a transfer of one or more first components or of a first layer onto a second substrate including: a) application and maintaining, by electrostatic effect, of the one or more first components or of the first layer, on a first substrate, made of a ferroelectric material, electrically charged, b) placing in contact, direct or by molecular adhesion, and transfer of the components or the layer onto a second substrate, and c) dismantling of the first substrate, leaving at least one part of the components or the layer on the second substrate.Type: GrantFiled: April 3, 2009Date of Patent: February 10, 2015Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Jean-Sebastien Moulet, Lea Di Cioccio, Marion Migette