Abstract: The present invention provides an array substrate, a method of fabricating the same, and a display module. The array substrate includes a substrate and a thin film transistor. An active layer of the thin film transistor includes: a first region including source and drain doped regions and a channel region; a second region surrounding at least a side of the channel region not in contact with the source and drain doped regions, and the first region forming a PN junction with the second region.

Abstract: A building automation system (BAS) includes building equipment located within a building and a BAS network configured to facilitate communications between the building equipment. The building equipment operate to affect a variable state or condition within the building. The BAS includes a BAS-BIM integrator configured to receive BAS points from the BAS network and to integrate the BAS points with a building information model (BIM). The BIM includes a plurality of BIM objects representing the building equipment. The BAS includes an integrated BAS-BIM viewer configured to use the BIM with the integrated BAS points to generate a user interface. The user interface includes a graphical representation of the BIM objects and the BAS points integrated therewith.

Abstract: The present disclosure relates to a method that includes applying a first perovskite precursor solution to a substrate to form a first liquid film of the first perovskite precursor solution on the substrate; from the first liquid film, forming a first intermediate solid perovskite layer on the substrate; repeating at least once, both the applying and the forming, resulting in the creation of at least one additional intermediate solid perovskite layer; and treating a last intermediate solid perovskite layer, resulting from the at least one additional applying and the at least one additional forming, to create a final solid perovskite layer.

Abstract: The present specification relates to a compound represented by Chemical Formula 1, a coating composition comprising the compound, an organic light emitting device formed using the coating composition, and a method for manufacturing the same.

Abstract: Structures for a non-volatile memory and methods of forming such structures. A gate electrode and a gate dielectric layer are formed over an active region with the gate dielectric layer between the gate electrode and the active region. A first doped region is formed in the active region, a second doped region is formed in the active region, and a source line is coupled to the second doped region. The first doped region is positioned in the active region at least in part beneath the gate dielectric layer, and the second doped region is positioned in the active region adjacent to the first doped region. The first doped region has a first conductivity type, and the second doped region has a second conductivity type opposite to the first conductivity type.

Abstract: This disclosure relates to image sensors and electronic apparatuses including the same. An image sensor including: a pixel area including shared pixels, wherein each of the shared pixels includes at least two photodiodes that form a group and share a floating diffusion (FD) area; and a transistor (TR) area adjacent to the pixel area, wherein the TR area includes transistor sets corresponding to the shared pixels, wherein, when a first shared pixel and a second shared pixel are arranged adjacent to each other in a first direction, a first TR set corresponding to the first shared pixel and a second TR set corresponding to the second shared pixel share a source region of a first selection TR.

Abstract: A light emitting device package including a partition structure having first and second surfaces, and first to third light emission windows penetrating through the first and second surfaces, a cell array including first to third light emitting devices on the first surface of the partition structure and overlapping the first to third light emission windows, each of the first to third light emitting devices including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, first and second wavelength conversion portions filling interiors of the first and second light emission windows, and having a meniscus-shaped interfaces, a first encapsulating portion including a light-transmissive organic film layer that fills the third light emission window and covers the first and second wavelength conversion portions, and a second encapsulating portion covering the first and second encapsulating portions and including a light-transmissive inorganic film layer.

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: Aspects describe gas sensitive field effect transistor (FET) structures, a gas sensitive FET array including the disclosed gas sensitive FET structures, and methods of manufacturing and using the same. In one example, a gas sensitive FET structure can include a body comprising a substrate layer, an intermediate layer over the substrate layer, and a passivation layer over the intermediate layer. Primary terminals disposed within the body can include at least one source terminal, at least one drain terminal and at least one gate terminal. A floating gate disposed within the body can comprise metal at a top surface of the intermediate layer. The passivation layer can be etched over the floating gate, and the floating gate can be electrically coupled to the gate terminal of the primary terminals. A sensing material layer can be positioned over the floating gate. A reset element can be included for resetting the floating gate.

Abstract: A metal interconnect arrangement in an integrated circuit, includes a damascene trench which includes a dielectric base, with a trench made therein, one or more two dimensional diffusion barrier layers formed over the trench, a conductor layer formed atop the diffusion layer, wherein the one or more two-dimensional diffusion barrier layers substantially prevent diffusion of constituents of the conductor layer into the dielectric base.

Abstract: A semiconductor device includes a first conductive pattern having a first line portion extending in a first direction and a first bending portion that extends from the first line portion. A closed area, surrounded by the first line portion and the first bending portion, is defined at one side of the first line portion. The semiconductor device further includes a second conductive pattern disposed in the closed area, the second conductive pattern being spaced apart from the first conductive pattern.

Abstract: A method is presented for reducing a reset current for a phase change memory (PCM). The method includes forming a bottom electrode, constructing a PCM cell structure including a plurality of phase change memory layers and a plurality of heat transfer layers, wherein the plurality of phase change memory layers are assembled in an alternating configuration with respect to the plurality of heat transfer layers, and forming a top electrode over the PCM cell structure. The plurality of phase change memory layers are arranged perpendicular to the top and bottom electrodes. Additionally, airgaps are defined adjacent the PCM cell structure.

Abstract: Methods for forming the semiconductor structure are provided. The method includes forming a fin structure and forming a gate dielectric layer across the fin structure. The method includes forming a work function metal layer over the gate dielectric layer and forming a gate electrode layer over the work function metal layer. The method further includes etching the work function metal layer to form a gap and etching the gate dielectric layer to enlarge the gap. The method further includes etching the gate electrode layer from the enlarged gap and forming a dielectric layer covering the gate dielectric layer, the work function metal layer, and the gate electrode layer. In addition, the dielectric layer includes a first portion, a second portion, and a third portion, and the first portion is thicker than the second portion, and the second portion is thicker than the third portion.

Abstract: Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.

Abstract: A building automation system (BAS) includes building equipment located within a building and a BAS network configured to facilitate communications between the building equipment. The building equipment operate to affect a variable state or condition within the building. The BAS includes a BAS-BIM integrator configured to receive BAS points from the BAS network and to integrate the BAS points with a building information model (BIM). The BIM includes a plurality of BIM objects representing the building equipment. The BAS includes an integrated BAS-BIM viewer configured to use the BIM with the integrated BAS points to generate a user interface. The user interface includes a graphical representation of the BIM objects and the BAS points integrated therewith.

Abstract: A semiconductor device is disclosed. The semiconductor device includes at least one row line arranged in a first direction over a cell array region, and at least one column line arranged in a second direction intersecting the first direction over the cell array region. The row line and the column line are configured to include conductive lines located at different levels and coupled to each other through a contact in the cell array region.

Abstract: A display panel, a manufacturing method thereof, and a display device are provided. The display panel includes: a first base substrate including a packaging region; a plurality of support portions located in the packaging region, a first interval being provided between adjacent support portions; a plurality of conductive lines located at a side of the plurality of support portions away from the first base substrate; a packaging layer located at a side of the plurality of conductive lines away from the first base substrate; and a second base substrate arranged opposite to the first base substrate and bonded with the first base substrate by the packaging layer.

Abstract: A mixer comprises a substrate of a first conductivity type; at least one minority carrier injector for injecting minority carriers in the substrate in reply to a first electrical signal applied to the at least one minority carrier injector; at least two substrate taps located in the substrate for providing a majority carrier current density with associated electric field in the substrate in reply to a second electrical signal applied to the at least two substrate taps. The majority carrier current density's associated electric field determines the drift direction of the injected minority carriers. The mixer further comprises at least two minority carrier collectors located in the substrate, for collecting minority carriers from the substrate. Each minority carrier collector is located adjacent to one of the at least two substrate taps.

Abstract: An OLED display panel, a method for manufacturing the same and an OLED display device are disclosed. The OLED display panel comprises a flat region and a curved region, wherein the OLED display panel comprises a light-emitting element in the flat region and a light-emitting element in the curved region, each light-emitting element comprises a cathode and an anode, and a distance between the anode and the cathode of the light-emitting element in the curved region is greater than a distance between the anode and the cathode of the light-emitting element in the flat region.

Abstract: An organic light emitting display device includes a substrate. A buffer layer is disposed on the substrate. The buffer layer includes a first opening exposing an upper surface of the substrate in a bending region. Pixel structures are positioned in a pixel region on the buffer layer. A fan-out wiring is positioned in the peripheral region and the pad region on the insulation layer structure such that the upper surface of the substrate and the first portion of the buffer layer are exposed. A passivation layer is disposed on the fan-out wiring, side walls of the insulation layer structure adjacent to the bending region, and the first portion of the buffer layer. The passivation layer includes a third opening exposing the upper surface of the substrate in the bending region. A connection electrode is positioned in the bending region on the substrate.