Abstract: A type of conditional probability fetcher prefetches data, such as for a cache, from another memory by maintaining information relating to memory elements in a group of memory elements fetched from the second memory. The information may be an aggregate number of memory elements that have been fetched for different memory segments in the group. The information is maintained responsive to fetching one or more memory elements from a segment of memory elements in the group of memory elements. Prefetching one or more remaining memory elements in a particular segment of memory elements from the second memory into the first memory occurs when the information relating to the memory elements in the group of memory elements indicates that a prefetching condition has been satisfied.

Abstract: A scheduling method of a scheduler that manages threads is executed by a computer. The scheduling method includes selecting a CPU of relatively less load, when a second thread is generated from a first thread to be processed; determining whether the second thread operates exclusively from the first thread; copying a first storage area assessed by the first thread onto a second storage area managed by the CPU, when the second thread operates exclusively; calculating based on an address of the second storage area and a predetermined value, an offset for a second address for the second thread to access the first storage area; and notifying the CPU of the offset for the second address to convert a first address to a third address for accessing the second storage area.

Abstract: Cache lines of a data cache may be assigned to a specific page type or color. In addition, the computing system may monitor when a cache line assigned to the specific page color is allocated in the cache. As each cache line assigned to a particular page color is allocated, the computing system may compare a respective index associated with each of the cache lines to determine maximum and minimum indices for that page color. These indices define a block of the cache that stores the data assigned to the page color. Thus, when the data of a page color is evicted from the cache, instead of searching the entire cache to locate the cache lines, the computing system uses the maximum and minimum indices as upper and lower bounds to reduce the portion of the cache that is searched.

Abstract: A computer-implemented method for increasing restore speeds of backups stored in deduplicated storage systems may include (1) identifying a backup that includes data stored in at least one data container within a deduplicated storage system, (2) detecting a subsequent backup that includes additional data, (3) calculating an amount of duplication between the additional data included in the subsequent backup and the data stored in the data container, (4) determining that the amount of duplication between the additional data and the data stored in the data container is below a predetermined threshold, (5) identifying at least one additional data container to store the additional data instead of deduplicating the additional data with respect to the data container, and then (6) storing the additional data in the additional data container to facilitate increasing a restore speed of the subsequent backup. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The present application provides a memory module. The memory module includes one or more volatile memory devices, one or more non-volatile memory devices, and a data exchange controller. The data exchange controller controls data exchange between the volatile memory devices and the non-volatile memory devices.

Abstract: Techniques are provided for using an intermediate cache to provide some of the items involved in a scan operation, while other items involved in the scan operation are provided from primary storage. Techniques are also provided for determining whether to service an I/O request for an item with a copy of the item that resides in the intermediate cache based on factors such as a) an identity of the user for whom the I/O request was submitted, b) an identity of a service that submitted the I/O request, c) an indication of a consumer group to which the I/O request maps, or d) whether the intermediate cache is overloaded. Techniques are also provided for determining whether to store items in an intermediate cache in response to the items being retrieved, based on logical characteristics associated with the requests that retrieve the items.

Abstract: Processes are disclosed for embodiments of a caching system to utilize a snapshot file or other limited size data structure to store a portion of the data stored in a cache. The snapshot file can be stored on persistent or otherwise non-transitory storage so that, even in case of a restart, crash or power loss event, the data stored in the snapshot file persists and can be used by the caching system after starting up. The snapshot file can then be used to restore at least some data into the cache in cases where the cached data in the cache is lost. For example, in cases of a cold-start or restart, the caching system can load data from the snapshot file into the empty cache. This can increase the number of cache hits since the cache is repopulated with useful data at startup.

Abstract: A tag unit configured to manage a cache unit includes a coalescer that implements a set hashing function. The set hashing function maps a virtual address to a particular content-addressable memory unit (CAM). The coalescer implements the set hashing function by splitting the virtual address into upper, middle, and lower portions. The upper portion is further divided into even-indexed bits and odd-indexed bits. The even-indexed bits are reduced to a single bit using a XOR tree, and the odd-indexed are reduced in like fashion. Those single bits are combined with the middle portion of the virtual address to provide a CAM number that identifies a particular CAM. The identified CAM is queried to determine the presence of a tag portion of the virtual address, indicating a cache hit or cache miss.

Abstract: A cache controller includes a first register that updates after every memory location swap operation on a number of cache sets in a cache memory and resets every N?1 memory location swap operations. N is a number of the cache sets in the cache memory. The memory controller also has a second register that updates after every N?1 memory location swap operations, and resets every (N2?N) memory location swap operations. The first and second registers track a relationship between logical locations and physical locations of the cache sets.

Abstract: A processor, operable in a computing storage environment, for each rank in a storage management device in the computing storage environment, allocates a lower maximum count, and a higher maximum count, of Task Control Blocks (TCBs) to be implemented for performing a storage operation, and performs the storage operation using up to the lower maximum count of TCBs, yet only allows those TCBs above the lower maximum count to be allocated for performing the storage operation satisfying at least one criterion.

Abstract: A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit may include multiple hash function sub-circuits, each of which applies a respective hash function to an input key value, producing a hash value. Each hash function sub-circuit may multiply bit vectors representing key values by a sparse bit matrix and may add a constant bit vector to the results. The hash function sub-circuits may be constructed using odd-parity circuits that accept as inputs subsets of the bits of the bit vectors representing the key values. The sparse bit matrices may be chosen or generated so that there are at least twice as many 0-bits per row as 1-bits or there is an upper bound on the number of 1-bits per row. Using sparse bit matrices in the hash function sub-circuits may allow the lookup circuit to perform lookup operations with very low latency.

Abstract: A method of monitoring, optimizing, and dynamically varying transfer size in a storage device is provided, including: receiving data transfer parameters for a Solid State Disk (SSD) device; selecting a data transfer size from the disk characterization data associated with the SSD device, based on a SSD device identifier in the received data transfer parameters matching the SSD device identifier in the disk characterization data; searching a weight-age table for a process identifier (PID) matching the PID from the received data transfer parameters; determining a heuristic representing a statistical distribution of Input/Output (I/O) operations per second (IOPS) and transfer sizes over time; modifying the received data transfer parameters based on at least one of: the selected data transfer size from the disk characterization data; the weight-age table; and the heuristic; and completing one or more (I/O) operations with the SSD device using the modified data transfer parameters.

Abstract: A controller receives a request to perform staging or destaging operations with respect to an area of a cache. A determination is made as to whether one or more discard scans are being performed or queued for the area of the cache. In response to determining that one or more discard scans are being performed or queued for the area of the cache, the controller avoids satisfying the request to perform the staging or the destaging operations with respect to the area of the cache.

Abstract: A computer system, comprising a server on which an application runs, and a storage system that stores data to be used by the application, the cache driver being configured to change, in a case of the condition of a cache area is a first cache condition in which data is readable from a cache area and writing of data into the cache area is prohibited, the condition of the cache area to a third cache condition in which reading of data from the cache area is prohibited and writing of data into the cache area is prohibited, from the first cache condition.

Abstract: Methods and structure for masking of logical unit numbers (LUNs) within a switching device coupled with one or more storage enclosures. Each storage enclosure defines one or more logical volumes each identified by a LUN within the storage enclosures. The switching device gathers LUN definition information regarding each LUN defined by each storage enclosure coupled with the switching device. LUN access permission information may be provided by an administrative node/user defining a level of access permitted or denied for each host system for each LUN for each storage enclosure. The switching device then intercepts a REPORT LUNS command from any host directed to a storage enclosure and responds with only those LUNs to which the requesting host system has permitted access. Further, any other SCSI command intercepted at the switching device directed to a LUN to which the host system does not have access is modified to identify an invalid LUN.

Abstract: A method of monitoring, optimizing, and dynamically varying transfer size in a storage device is provided, including: receiving data transfer parameters for a Solid State Disk (SSD) device; selecting a data transfer size from the disk characterization data associated with the SSD device, based on a SSD device identifier in the received data transfer parameters matching the SSD device identifier in the disk characterization data; searching a weight-age table for a process identifier (PID) matching the PID from the received data transfer parameters; determining a heuristic representing a statistical distribution of Input/Output (I/O) operations per second (IOPS) and transfer sizes over time; modifying the received data transfer parameters based on at least one of: the selected data transfer size from the disk characterization data; the weight-age table; and the heuristic; and completing one or more (I/O) operations with the SSD device using the modified data transfer parameters.

Abstract: Exemplary methods, apparatuses, and systems receive a first request for a storage address at a first access time. Entries are added to first and second data structures. Each entry includes the storage address and the first access time. The first data structure is sorted in an order of storage addresses. The second data structure is sorted in an order of access times. A second request for the storage address is received at a second access time. The first access time is determined by looking up the entry in first data structure using the storage address received in the second request. The entry in the second data structure is looked up using the determined first access time. A number of entries in second data structure that were subsequent to the second entry is determined. A hit count for a reuse distance corresponding to the determined number of entries is incremented.

Abstract: System and methods are provided for dynamically determining accesses to memory areas in a memory system. An example system includes a first plurality of tracking units, a second plurality of tracking units, and a controller. The first plurality of tracking units are configured to determine accesses to multiple memory areas during a first time period and select one of the memory areas based at least in part on the determined accesses to the memory areas, a memory area including multiple sub-areas. The second plurality of tracking units are configured to determine accesses to the sub-areas of the selected memory area during a second time period. The controller is configured to generate information related to the determined accesses to the memory areas and the sub-areas in the selected memory area for memory management.

Abstract: Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.

Abstract: Systems and methods for predictive cache replacement policies are provided. In particular, some embodiments dynamically capture and predict access patterns of data to determine which data should be evicted from the cache. A novel tree data structure can be dynamically built that allows for immediate use in the identification of developing patterns and the eviction determination. In some cases, the data can be dynamically organized into histograms, strings, and other representations allowing traditional analysis techniques to be applied. Data organized into histogram-like structures can also be converted into strings allowing for well-known string pattern recognition analysis. The pattern recognition and prediction techniques disclosed also have applications outside of caching.