Abstract: System and methods are provided for dynamically determining accesses to memory areas in a memory system. An example system includes a first plurality of tracking units, a second plurality of tracking units, and a controller. The first plurality of tracking units are configured to determine accesses to multiple memory areas during a first time period and select one of the memory areas based at least in part on the determined accesses to the memory areas, a memory area including multiple sub-areas. The second plurality of tracking units are configured to determine accesses to the sub-areas of the selected memory area during a second time period. The controller is configured to generate information related to the determined accesses to the memory areas and the sub-areas in the selected memory area for memory management.

Abstract: Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.

Abstract: Systems and methods for predictive cache replacement policies are provided. In particular, some embodiments dynamically capture and predict access patterns of data to determine which data should be evicted from the cache. A novel tree data structure can be dynamically built that allows for immediate use in the identification of developing patterns and the eviction determination. In some cases, the data can be dynamically organized into histograms, strings, and other representations allowing traditional analysis techniques to be applied. Data organized into histogram-like structures can also be converted into strings allowing for well-known string pattern recognition analysis. The pattern recognition and prediction techniques disclosed also have applications outside of caching.

Abstract: Systems and methods for reducing problems and disadvantages associated with protecting data during cold excursions are provided. A method for preventing unreliable data operations at cold temperatures may include determining whether a first temperature of a solid state drive (SSD) is below a threshold temperature. The method may also include initiating an artificial read/write operation if the first temperature is below the threshold temperature.

Abstract: A device may receive information identifying an attribute to be used when determining whether to archive a digital message. The attribute may be associated with the digital message. The device may determine an attribute value based on the attribute and the digital message. The device may determine an archival weight corresponding to the attribute. The device may compute an archival score for the digital message. The archival score may be based on the attribute value and the archival weight. The device may determine that the archival score satisfies a threshold. The device may archive the digital message based on determining that the archival score satisfies the threshold.

Abstract: A method is used for managing cache backup and restore for continuous data replication and protection. I/O operations are quiesced at a cache module. A first snapshot of a storage object and a second snapshot of an SSD cache object are taken. The I/O operations at the cache module are unquiesced. A single backup image comprising the first snapshot and the second snapshot is created. The single backup image is sent to a first data protection appliance (DPA) and recorded in a journal.

Abstract: Systems and methods for wiping and verifying the wiping of a data storage device where the dirtying of blocks of the storage device is tracked and only the dirtied blocks are scanned to verify if the storage device has been sufficiently wiped.

Abstract: A mechanism for reducing power consumption of a cache memory of a processor includes a processor with a cache memory that stores instruction information for one or more instruction fetch groups fetched from a system memory. The cache memory may include a number of ways that are each independently controllable. The processor also includes a way prediction unit. The way prediction unit may enable, in a next execution cycle, a given way within which instruction information corresponding to a target of a next branch instruction is stored in response to a branch taken prediction for the next branch instruction. The way prediction unit may also, in response to the branch taken prediction for the next branch instruction, enable, one at a time, each corresponding way within which instruction information corresponding to respective sequential instruction fetch groups that follow the next branch instruction are stored.

Abstract: In one embodiment, a computer system includes a cache having one or more memories and a metadata service. The metadata service is able to receive requests for data stored in the cache from a first client and from a second client. The metadata service is further able to determine whether the performance of the cache would be improved by relocating the data stored in the cache. The metadata service is further operable to relocate the data stored in the cache when such relocation would improve the performance of the cache.

Abstract: Embodiments of a method and apparatus for monitoring activity on a virtual machine are generally described herein. The activity may be monitored by a first hypervisor and the virtual machine may be controlled by a second hypervisor. In some embodiments, the method includes setting a breakpoint in a kernel function of the virtual machine. The method may further include generating a page fault, responsive to the virtual machine halting execution at the breakpoint, to cause the second hypervisor to page in contents of a memory location accessed by the kernel function. The method may further include inspecting the contents of the memory location to detect activity in the virtual machine.

Abstract: A row buffer 102 in DRAM 100 stores any data read from a memory array 101 in a specified data length unit. An LLC 206 is cache memory, and extracts and stores a part of data stored in the row buffer 102 as cache data. In a MAC 701, when push-out control of the LLC 206 is performed, it is predicted that data at which DIMM address is stored in the row buffer 102 in the near future based on the queuing state of an MRQ 203. In the MAC 701, each physical address of the cache data in a push-out target range 702 on the LLC 206 is converted into a DIMM address. If the converted address matches the predicted address of the data, then the cache data corresponding to the matching addresses is pushed out on a priority basis from the LLC 206.

Abstract: System and methods are provided for building redundancy data of a source storage medium using a redundant-array-of-independent-disks (RAID) array, the RAID array including one or more target storage mediums, the source storage medium including multiple data areas. One or more invalid data areas on the source storage medium are identified. Identification information of the one or more invalid data areas is generated. Redundancy data for data areas on the source storage medium other than the one or more invalid data areas is built using the RAID array.

Abstract: A flush control apparatus controls a Set Associative cache memory apparatus. A flush control apparatus includes: a tag memory unit associating a tag identifier identifying a tag which associates a plurality of cache lines and tag information representing whether or not the tag is valid. It also includes a line memory unit, a way specification unit and a flush unit which flushes the way specified by the way specification unit.

Abstract: A storage device includes a plurality of magnetic disk devices each having a write cache, a processor unit that redundantly stores data, a rebuild execution control unit that performs a rebuild process, a write cache control unit that, at the time of the rebuild process, enables a write cache of a storage device that stores rebuilt data, and a rebuild progress management unit that is configured using a nonvolatile memory and manages progress information of the rebuild process. In the case where power discontinuity is caused during the rebuild process and then power is restored, the rebuild execution control unit calculates an address that is before an address of last written rebuilt data by an amount corresponding to the capacity of the write cache based on the progress information of the rebuild process managed by the progress management unit and resumes the rebuild process from that calculated address.

Abstract: According to one embodiment a memory system includes a circuit card and a separable area array connector on the circuit card. The system also includes a memory device positioned on the circuit card, wherein the memory device is configured to communicate with a main processor of a computer system via the area array connector.

Abstract: Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.

Abstract: A memory controller includes: a determination part configured to determine a type of a DIMM having a different address line topology based on SPD; a slew rate setting part configured to set a slew rate of an address signal based on the type of the DIMM determined by the determination part; and a delay setting part configured to set a data delay amount when reading/writing data.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage device, a first storage module, a second storage module, a controller, a random number generator, and a randomizing module. The first storage module stores a plurality of management data. The second storage module stores seed data. The controller issues a first command to designate one of the management data, and issues a second command to command writing in or reading from the storage device. The random number generator generates random number data, by shuffling the seed data, based on the management data that is designated by the first command. The randomizing module randomizes written data or read data, based on the random number data.

Abstract: An embodiment for reusing data in content files includes receiving a request for a content file and retrieving a recipe that includes a series of instructions needed to compose the content file. Data identified by the recipe may then be retrieved from a content file server and the requested content file is composed based on the set of instructions in the recipe. In an example, the recipe is processed by a recipe player to compose a content file. In another embodiment, content files are stored in a cache as a series of instructions for generating them from portions of other content files. In this way, performance in a content delivery network may be improved by reusing similar data in content files.

Abstract: Efficient techniques are described for extending the usable lifetime for memories with limited write endurance. A technique for wear-leveling of caches addresses unbalanced write traffic on cache lines which cause heavily written cache lines to fail much fast than other lines in the cache. A counter is incremented for each write operation to a cache array. A line affected by a current write operation which caused the counter to meet a threshold is evicted from the cache rather than writing data to the affected line. A dynamic adjustment of the threshold can be made depending on the operating program. Updates to a current replacement policy pointer are stopped due to the counter meeting the threshold.