Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.

Abstract: An IC structure includes a source epitaxial structure, a drain epitaxial structure, a first silicide region, a second silicide region, a source contact, a backside via rail, a drain contact, and a front-side interconnection structure. The first silicide region is on a front-side surface, a first sidewall of the source epitaxial structure, and a second sidewall of the source epitaxial structure. The second silicide region is on a front-side surface of the drain epitaxial structure. The source contact is in contact with the first silicide region and has a protrusion extending past a backside surface of the source epitaxial structure. The backside via rail is in contact with the protrusion of the source contact. The drain contact is in contact with the second silicide region. The front-side interconnection structure is on a front-side surface of the source contact and a front-side surface of the drain contact.

Abstract: An IC includes: a plurality of first cells placed in a series of first rows extending in a first horizontal direction and each having a first height; and a plurality of second cells placed in a series of second rows extending in the first horizontal direction and each having a second height different from the first height, wherein a total height of the series of first rows corresponds to a multiple of a height of a first multi-height cell with a maximum height among the plurality of first cells, and a total height of the series of second rows corresponds to a multiple of a height of a second multi-height cell with a maximum height among the plurality of second cells.

Abstract: A semiconductor device includes a buried communication (com) conductor (BC) CFET including: first and second active regions arranged in a stack according to CFET-type configuration; a first layer of metallization (M_1st layer) over the stack which includes first conductors configured for data or control signals (communication (com) conductors), and power grid (PG) conductors; and a layer of metallization (M_B layer) below the stack and which includes second com conductors.

Abstract: A semiconductor structure includes a substrate and a fin protruding from the substrate along a first direction, wherein the fin includes a first semiconductive layer over the substrate, a second semiconductive layer over the first semiconductive layer along the first direction, and a dielectric layer disposed between the first semiconductive layer and the second semiconductive layer and electrically isolated from the first semiconductive layer and the second semiconductive layer. The semiconductor structure also includes a gate electrode including: a first conductive portion extending in a second direction different from the first direction and including an upper surface level with an upper surface of the first semiconductive layer; and a second conductive portion electrically isolated from the first conductive portion and including a bottom surface level with a bottom surface of the second semiconductive layer.

Abstract: The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair of source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.

Abstract: Various semiconductor techniques described herein enable reductions in one or more sizes of a fin field-effect transistor (finFET) and/or increasing one or more sizes of a finFET. In various implementations described herein, a material may be used to reduce the one or more x-direction sizes of the finFET by selective deposition while enabling the one or more y-direction sizes of the finFET to be increased or enlarged by etching. The x-direction size of a source or drain of the finFET, the x-direction size of an active region of the finFET, and/or the x-direction size of a polysilicon region of the finFET may be increased by selective deposition of a boron nitride (BxNy), a boron carbide (BxC), a boron oxide (BxOy) (e.g., boric oxide (B2O3), a fluorocarbon (CxFy) polymer, and/or another material.

Abstract: A package structure includes a circuit substrate, a semiconductor package, a thermal interface material, a lid structure and a heat dissipation structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The thermal interface material is disposed on the semiconductor package. The lid structure is disposed on the circuit substrate and surrounding the semiconductor package, wherein the lid structure comprises a supporting part that is partially covering and in physical contact with the thermal interface material. The heat dissipation structure is disposed on the lid structure and in physical contact with the supporting part of the lid structure.

Abstract: Example embodiments relate to methods for inducing stress in semiconductor devices. One method includes a method for producing a first semiconductor device and a second semiconductor device configured to conduct current through the controlled density of charge carriers in a channel area. The charge carriers of the first semiconductor device have opposite polarity to the charge carriers of the second semiconductor device. The method includes producing a stress relaxed buffer (SRD) layer. The back side of the SRB layer is positioned on a substrate. The method also includes producing a semiconductor layer on the front side of the SRB layer. Additionally, the method includes producing the first semiconductor device and the second semiconductor device on the semiconductor layer, removing the substrate, thinning the SRB layer, producing a cavity in the SRB layer, and filling the cavity with a material to create a stress compensation area.

Abstract: An integrated circuit includes at least one decoupling cell, wherein the at least one decoupling cell includes at least one P-type decoupling MOSFET and at least one N-type decoupling MOSFET, and a number of the at least one P-type decoupling MOSFET is different from a number of the at least one N-type decoupling MOSFET.

Abstract: Provided is a semiconductor device including a substrate, one hybrid fin, a gate, and a dielectric structure. The substrate includes at least two fins. The hybrid fin is disposed between the at least two fins. The gate covers portions of the at least two fins and the hybrid fin. The dielectric structure lands on the hybrid fin to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the hybrid fin. The hybrid fin includes a first portion, disposed between the two segments of the gate; and a second portion, disposed aside the first portion, wherein a top surface of the second portion is lower than a top surface of the first portion.

Abstract: A semiconductor structure includes a first semiconductor device formed over a substrate and a second semiconductor device formed over the substrate. The first semiconductor device includes a first source/drain feature over the substrate, a first gate structure over the substrate, a first conductive feature over the first source/drain feature, and a first insulation layer between the first gate structure and the first conductive feature. The second semiconductor device includes a second source/drain feature over the substrate, a second gate structure over the substrate, a second conductive feature over the second source/drain feature, and a second insulation layer between the second gate structure and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are different, and a width of the first insulation layer is less than a width of the second insulation layer.

Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

Abstract: A method of forming a semiconductor structure includes forming a first top electrode (TE) layer over a magnetic tunnel junction (MTJ) layer and performing a smoothing treatment on the first TE layer. The smoothing treatment is performed in situ after the forming first TE layer. The smoothing treatment removes spike point defects from the first TE layer. Additional TE layers may be formed over the first TE layer.

Abstract: A method comprises removing a portion of molding compound from a side of a package structure by a laser ablation process to create an opening that exposes a portion of a conductive clip, depositing solder paste on the exposed portion of the conductive clip, and reflowing the solder paste. The laser ablation process in one example is a pulsed laser ablation process that includes raster scanning a laser along a portion of the side of the package structure to create the opening. Depositing the solder paste in one example includes performing a dispense process or a screening process that deposits solder paste in the opening onto the exposed portion of the conductive clip.

Abstract: Embodiments of the present disclosure provide an OLED device, a method of manufacturing the OLED device, and a display panel. The OLED device comprises: a substrate, a first electrode layer, a color filter layer, a light emitting layer and a second electrode layer. The first electrode layer is one of an anode layer or a cathode layer and comprises: a first sub-electrode layer disposed on the substrate; and a second sub-electrode layer electrically connected with the first sub-electrode layer. The color filter layer is disposed on the first sub-electrode layer and the second sub-electrode layer is disposed on the color filter layer. The second electrode layer is the other of the anode layer or the cathode layer and the light emitting layer is disposed between the second electrode layer and the second sub-electrode layer of the first electrode layer.

Abstract: A method for calibration including determining a temperature induced offset in a pedestal of a process module under a temperature condition for a process. The method includes delivering a wafer to the pedestal of the process module by a robot, and detecting an entry offset. The method includes rotating the wafer over the pedestal by an angle. The method includes removing the wafer from the pedestal by the robot and measuring an exit offset. The method includes determining a magnitude and direction of the temperature induced offset using the entry offset and exit offset.

Abstract: A semiconductor device includes first and second vertical transport field-effect transistor (VTFET) devices. Each of the first and second VTFET devices includes a bottom epitaxial layer, a plurality of channel fins formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed between the channel fins, a high-? metal gate formed between the channel fins and the first ILD layer, a top epitaxial layer formed discretely on each of the channel fins, and a trench epitaxial layer formed continuously across the top epitaxial layer, a portion of the first ILD layer also being formed between the first and second VTFET device. The semiconductor device also includes a second ILD layer formed on the portion of the first ILD layer that is between the first and second VTFET devices, the second ILD layer separating the top epitaxial layers of the first and second VTFET devices.

Abstract: A device includes a substrate, a channel layer, a gate structure, a source/drain epitaxial structure, and a bottom dielectric structure. The channel layer is over the substrate. The gate structure is over the substrate and surrounds the channel layer. The source/drain epitaxial structure is over the substrate and is connected to the channel layer. The bottom dielectric structure is between the source/drain epitaxial structure and the substrate.

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures that provide metal gate N/P boundary control in an integrated circuit (IC) using an active gate cut and recess processing scheme. In a non-limiting embodiment of the invention, a gate cut is formed in an N/P boundary between an n-type field effect transistor (FET) and a p-type FET. A first portion of a first work function metal is removed over a channel region of the n-type FET. The gate cut prevents etching a second portion of the first work function metal. The first portion of the first work function metal is replaced with a second work function metal. The gate cut is recessed, and a conductive region is formed on the recessed surface of the gate cut. The conductive region provides electrical continuity across the N/P boundary.