Abstract: In a data transmission system in which a plurality of stations each including a processor are interconnected by links, each processor is constituted by a memory device, which when receives a command containing a program from other station, stores a program contained in the command from a predetermined address, a register which, when receives the command representing a condition of starting the program, stores the information, an addressing circuit supplying an address signal to the memory device, a comparator comparing with each other the outputs of the addressing circuit and the register and a subroutine call means for executing the program when the output of the comparator shows a coincidence.

Abstract: A method to operate on a single instruction multiple data (SIMD) computer for searching for relevant documents in a database which makes it possible to perform thousands of operations in parallel. The words of each document are stored by surrogate coding in tables in one or more of the processors of the SIMD computer. To determine which documents of the database contain a word that is the subject of a query, a query is broadcast from a central computer to all the processors and the query operations are simultaneously performed on the documents stored in each processor. The results of the query are then returned to the central computer. After all the search words have been broadcast to the processors and point values accumulated as appropriate, the point values associated with each document are reported to the central computer. The documents with the largest point values are then ascertained and their identification is provided to the user.

Abstract: An operator console for data communication is divided into two separate units which can be connected electrically together, namely a keyboard (10) having a logical unit (21), with a memory (211) and a ciphering/deciphering circuit (22), and a security module (11). Connected between the input side of the keyboard (10) and the memory (211) is a security circuit which disconnects a conduit (240) to the keyboard memory (211), subsequent to a first transfer of a code from the security module (11), and connects instead a conductor (241) to the memory (211) from the ciphering/deciphering circuit (22).

Abstract: An electronic calendaring method for use in a data processing system in which calendar entries that have been made for the same time span independently on two different copies of the calendar can be automatically and interactively reconciled. The method permits a calendar owner to obtain a machine readable transportable copy of his calendar on a diskette, to update that copy when the master copy is not available to him because of a business trip, for example, and upon his return to automatically and interactively reconcile the updated entries that have been made to both copies so that at least one of them reflects the correct status of calendered events for that owner.

Abstract: A plurality of parallel processing elements are connected in a binary tree configuration, with each processing element except those in the highest and lowest levels being in communication with a single parent processing element as well as first and second (or left and right) child processing elements. Each processing element comprises a processor, a read/write or random access memory, and an input/output (I/O) device. The I/O device provides interfacing between each processing element and its parent and children processing elements so as to provide significant improvements in propagation speeds through the binary tree. The I/O device allows the presently preferred embodiment of the invention to be clocked at 12 megahertz, producing in the case of a tree of 1023 processors, each having an average instruction cycle time of 1.8 .mu.s, a system with a raw computational throughput of approximately 570 million instructions per second.

Abstract: A pipelined data processor comprises a circuit for storing two instructions in a pair of instruction registers, a circuit for detecting whether those instructions are a combination of an instruction requesting the use of an operation unit and an instruction requesting the use of another resource, and a circuit to control the execution of the instructions when the decision of the detection circuit is affirmative such that those instructions are executed by the operation unit and the resource in a plurality of stages.

Abstract: An improved display controller provides commands for changing a display. The controller includes a component for determining whether or not the command provided thereby includes an attribute changing command therein. If a NOCHANGE mode has been set, and the controller component determines that an implicit attribute changing command is included in the display command, the attribute changing command is inhibited. If a direct, explicit, attribute changing command is detected, the attribute change is performed. If the NOCHANGE mode has not been set, all attribute changing commands are executed, whether implicitly or explicitly provided.

Abstract: A VSAM data set is moved to another DASD volume in less time than that required by logical processing by invoking a DASD track-oriented process extrinsic to VSAM which can select and order the transfer of VSAM components to a newly created VSAM cluster.

Abstract: An electronic business terminal has the capability of electronically displaying a plurality of individual journal entry items on a CRT at the command of the terminal operator, who can cause the display of items to be scrolled backward or forward as desired, to locate a particular journal item. The information to be displayed is stored in a journal window stack. Controls are provided for determining the address of the initial entry of the stack, the size of the stack and the location at which the next item is to be added to the stack. Controls are also provided for display of the entries contained in the stack. A counter is provided to count the number of entries in the stack.

Abstract: A system for programming a computer provides a set of software-based virtual machines each for instructing a computer to carry out a selected operation. Each virtual machine is represented by a virtual front panel displayed on a screen and each virtual front panel graphically displays operator controllable values of input and output parameters utilized by the virtual machine it represents. The system is adapted to synthesize a new virtual machine for instructing the computer to perform a sequence of operations wherein each operation is carried out by the computer according to the instructions of an operator selected one of the existing virtual machines. The system also creates a new virtual front panel for displaying input and output parameters associated with the new virtual machine. The system permits the operator to program the computer by directing synthesis of a hierarchy of virtual machines.

Abstract: A digital signal processor includes a global RAM that is accessable by an external high priority bus, a microprocessor and an I/O controller. The global RAM is accessed by a global address bus and a global data bus. The global address bus is coupled by separately selectable buffers to a microprocessor address bus, the external address bus, and an I/O bus, respectively. The global data bus is coupled by separately selectable transceivers to the microprocessor data bus, the external bus, and the I/O bus, respectively. Either the microprocessor or the I/O port controller may request and be granted access to the global memory at any time if it is not already being accessed. If the external bus requests access to the global RAM and either the microprocessor or the I/O port controller is accessing the global RAM, multiple wait states are inserted into that microprocessor or I/O port controller until the external bus completes its access.

Abstract: A microprocessor and a peripheral equipment communicate data through a bus. If an error occurs during communication, the microprocessor starts the next bus cycle and commands retry of the data communication. If a predetermined number of times of retry fail, and if an address signal corresponds to an unmounted area of an address space, wherein the unmounted area is an area of the address space not occupied by peripheral equipment including an I/O device, the microprocessor inhibits the retry.

Abstract: A computer controlled radio communications device (e.g. a radio) having functional characteristics such as operating frequencies (i.e. a "personality") determined, at least in part, by characteristic-defining stored digital data and having the ability to automatically transmit/receive such characteristic/defining stored digital data to/from a similar computer-controlled radio communications device so as to provide another device having similar functional characteristics (i.e. a "cloned" device). A special unidirectional data transfer wiring harness is preferably used in conjunction with externally accessible plug connectors on each device to temporarily effect the requisite interconnection between the devices during such a personality "cloning" process.

Abstract: A multiprocessor system includes a number of subsystems all coupled in common to an asynchronous system bus. Apparatus is included in the system bus interface logic of each processing subsystem to receive commands from the system bus and compare the interrupt priority level of the new command with the current command being executed. If the new command has a lower interrupt priority than the current command, then the subsystem sending the command will receive a not acknowledge response from the processing system. The apparatus is responsive to certain control signals from the new command to bypass the interrupt priority comparison logic and initiate an immediate interrupt regardless of the interrupt priority level of the current command being executed by the processing subsystem. The processing subsystem may also generate a command to itself via the system bus which requires the high speed interrupt.

Abstract: A compiling method is provided for vectorizing outer sides of multiple loops which are not tight. The method detects variables which are defined in one loop and referenced by another. The information, mapped into a dependence graph, is used to analyze the data dependency of each loop level and expand the source program. The value of the variable is substituted for an appropriate element of the array and the value of the appropriate element of the array is substituted for an original variable. The compiler inserts control statements to assure initial values and end values for the loops are preserved minimizing the size of the working arrays, and vectorizing multiple loops for each loop level.

Abstract: A resource sharing system including one or more resources, a plurality of resource access devices for accessing the resources, a priority order holder for holding a priority order for access competition between the resources and the resource access device, an ordering device for ordering the access competition in accordance with the priority order held in the holder, and priority order changer for raising the priority order of one access device if a low priority order access is not accepted by the one access device a predetermined number of times.

Abstract: An instruction having two operands includes a field specifying the bit length of a source operand and a field specifying the bit length of data to be operated upon by the execution unit. Based on size information stored in these fields, the operand bit length is modified, which avoids need for modification of the bit length of an operand by use of a macro instruction at the time of execution of an operation based on the two operands. Consequently, the program execution speed can be improved.

Abstract: A database processing device executes concurrent processing in accessing a database through a plurality of independent terminal units. The database processing device, upon updating data stored in a record after reading out the data stored in the record in the database and correcting or altering the data through a specific terminal, confirms whether or not the data stored in the record has been updated by terminals, and executes updating only when the data has not been updated. The data stored in the record includes update control information for confirming whether or not the data has been updated by other terminals.

Abstract: At an occurrence of an interrupt, each entry of the vector table of the vitrual machine monitor to be referenced by the hardware of the bare machine is loaded with an address of an interrupt processing program of the running virtual machine for an interrupt number associated with the entry. When the interrupt is allowed to be directly processed by the virtual machine, the virtual machine monitor is not activated, that is, the interrupt processing program of the vitual machine can immediately execute the necessary processing, which eliminates the overhead associated with the intervention of the virtual machine monitor. Moreover, the content of the system stack pointer is set to point to the stack of the running virtual machine. Consequently, the content of the registers to be saved for an interrupt processing are directly stored in the stack of the running virtual machine, and therefore the overhead caused because the stack of the virtual machine monitor is used is removed.

Abstract: A peripheral interface system is disclosed. An input-output processor is provided to receive input-output commands from a central processing unit. Up to four multiplexing units may be connected to the input-output processor, with each multiplexing unit providing an interface for up to four controller units, which may be used to control a peripheral device. The multiplexing unit includes a pair of data buffers, each with its own addressing circuit, and each functionally divided into four storage areas, each storage area providing four registers to store four parcels of data. Data is transferred between the input-output processor and the controller units by filing the storage area in a buffer from the local memory of the input-output processor in a serial fashion over a DMA channel provided between the multiplexer and the local memory.