Abstract: A portable electronic typewriter having a memory incorporating a low-cost spelling-check dictionary and including a multi-character display. The typewriter is operable in a "List" mode according to which the operator can call up display of a portion of the dictionary, sequentially in alphabetical order and one word at a time. The display consists of each stored word sharing an initial set, or "string", of n characters (termed a "template") defined by the operator via the keyboard of the typewriter. In a preferred version, when the typist becomes aware of uncertainty as to spelling, the List Mode may be initiated either before or after partial entry of the desired word. In particular, if the characters entered include an erroneous one, (the typist being alerted of this by an audible alarm, for example), initiation of the List Mode thereafter causes the string to be truncated just before the erroneous character.

Abstract: An apparatus is included within the bus interface circuits of each processing unit of a multiprocessing system which connect in common with the other units of the system to an asynchronous system bus. The apparatus and interrupt signal couple to the processing unit's level register and interrupt circuits. In response to a command specifying a level change, the apparatus conditions these circuits to store level and interrupt signals applied to the system bus as part of such CPU command during a bus cycle of operation granted to the processing unit on a priority basis. This ensures the reliable switching between interrupt levels and the notification of such level changes to the other units of the system without interference from other processing units.

Abstract: An address generator for generating addresses for target locations in a circular buffer of length L, the buffer having an upper boundary and a lower boundary, the lower boundary being at an address which is a multiple of an integer power of two, and the address of a target location being offset by M locations from a current buffer location at address A, where M is no longer than L. The apparatus comprises a set of three registers, an adder for generating an absolute address, an adder/subtractor for generating a wrapped address which maps the absolute address into the buffer address space when the absolute address is outside that space, and certain control logic for selecting as the target address either the absolute address or the wrapped address. The contents of the three registers represent, respectively, the length of the buffer, the current address designated by the pointer, and the offset from the current buffer address to the target location in the buffer.

Abstract: In a data processing system, each direct memory access controller is connected to a bus and the memory it controls, the memory being connected to a bus, bypassing the controller. The controller simultaneously generates two addresses, one for addressing the memory space it controls and another for addressing memory space controlled by another controller. Data is then passed directly from one memory space over the bus to another memory space in a single clock cycle. When a controller is acting as a bus master it causes the generation of a system, user or external signal signifying what memory space it will be permitted to access and each controller includes comparison circuits for comparing an address on the bus with one or more address space limit values, depending upon which of the three signals is received. An error signal is produced by the controller if another controller attempts to address memory space which it is not permitted to access.

Abstract: Method and apparatus for temporarily storing multiple data records in a data processing system which includes a host computer, a cache buffer subsystem, and a magnetic tape drive subsystem. A microprocessor, acting in part as a cache manager, directs the transfer of data into and out of a memory in the cache buffer subsystem by setting up a fill address register, a drain address register, and a start of record address register. Through utilization of a CRC byte to detect errors without correction, and a stop bit to locate the end of a record, values of the registers are compared dependent upon whether there is data being filled or drained to properly manage the temporary storage of data within the memory.

Abstract: A combination FIFO buffer and programmable shift register having asynchronous input and output capabilities comprises a three stage system which synchronizes the incoming data stream with the memory input clock, buffers the incoming data stream and provides a variable delay for the data. The digital data stream from an input device is received by an input synchronizer having its input clocked at the clock rate of the input device clock and its output clocked at a higher internal clock rate. The data is written into two FIFO buffers, a master and a slave. The master buffer controls the read and write addresses of both buffers, so that the write address of the buffers advances only when valid data is written into the buffers, and the read address advances only when data is read out of the buffers. The slave buffer can be programmed with an offset in its read address, so it operates as a delay buffer.