Abstract: A Java-based method for performing Boundary-Scan Test procedures on an IEEE Standard 1149.1 compliant integrated circuit device. A Boundary-Scan Test application procedural interface (BST API) is provided that includes several objects defining the Boundary-Scan architecture of IEEE Standard 1149.1 compliant integrated circuit devices, and defines a plurality of Java-based source code commands utilized in applets for performing Boundary-Scan Test procedures. To facilitate implementing a single applet on a wide variety of hardware platforms, the BST API is based on a command structure subset implemented by a wide range of available Java flavors.

Abstract: A process and apparatus for synchronizing the block counter of an RDS radio data receiver is described. According to the process, the bits stored in a 26-bit shift register, are cycled at least n times in said register, n being the number of allowable offset words, and the shift register content is X-OR gated with another offset word in a given sequence for each cycle. The gating result is received by a syndrome detection circuit, which triggers a sync pulse when the zero syndrome is detected, and the sync pulse resets the bit counter to zero and sets the block counter to the address counter status assigned to the offset word in the offset word generator.

Abstract: A Reed Solomon error correction code calculator is disclosed, that comprises a plurality of modules, each of which has a memory, a matrix calculator, and an exclusive-OR circuit, the plurality of modules being cascade connected, and at least one register disposed between each of the plurality of modules.

Abstract: The specification relates to a method and an apparatus for generating cyclical redundancy code (CRC) by analyzing segmented groups of bits from a message concurrently, producing a temporary remainder value as a result of a multiple bit lookup from a generating CRC lookup table, using the temporary remainder or a portion thereof along with the next sequential segmented group of message bits as exclusive-or inputs, taking the result of the exclusive-or output and applying the result as a lookup value from the generating CRC lookup table. The process is repeated until the message groups have been depleted, at which time the message is completely coded and the temporary remainder existing at the time represents the CRC checkbits for the message. The recursive method developed in association with the present invention is called a Recursive Syndrome Expansion (RSE).

Abstract: A demodulator for digital-versatile disk (DVD) optical disks converts 16-bit codewords stored on the disk into 8-bit symbols or user bytes that are sent to the host after error correction. Rather than use the modulation tables in the DVD specification in reverse, the entries in the modulation table are sorted and combined. The four states stored in the DVD modulation table are reduced to two states or conditions. All entries from states 1 and 4 are sorted into unique tables that have unique mappings of codewords to symbols. Since the unique mappings are not sequence or state dependent, no state information is stored in the unique tables. Entries from states 2 and 3 are sorted into duplicates tables that have duplicate mappings, where a codeword can map to two different symbols, depending on the state sequence. One of the two symbols is chosen based on bits in the following codeword, which is the next state.

Abstract: A digital signal processor (DSP), hardware module, and shared memory coupled together to perform Viterbi decoding on a sequence of received symbols. Given channel coefficients, the DSP calculates initial data for Viterbi processing: combination values for each possible state and branch product values for each possible symbol. These values are stored in shared memory for access by the hardware module. The DSP further calculates the first few stages of the Viterbi processing so path metrics are well defined for every state. Path metric values are also stored into the shared memory. The hardware module is optimized to perform calculations associated with a single stage of the Viterbi algorithm. The DSP invokes by the hardware module by passing a received sample to the hardware module. The hardware module calculates a survivor state value and minimizing path metric value for each state in the state space.

Abstract: To provide a microprocessor that can perform high-speed CRC code generation and can be implemented simply and at a low cost, a microprocessor has, at a part of a data input path to a shift circuit which is conventionally installed in an ALU of the microprocessor to execute shift commands, one bit of data that corresponds to the path, an exclusive OR circuit, which computes the exclusive OR of an uppermost bit of byte data and a bit data, is provided. For this circuit, a result according to a generating polynomial such as [X8+X4+X3+X2+1] is determined on the basis of the installation location of the exclusive OR circuit along the path, and by setting an initial value to the byte data, inputting one bit of the transmission data sequentially to the bit data and operating the shift circuit, a computed result for the CRC code is derived. Consequently, for the microprocessor, the CRC code can be generated at a high speed using the computation commands of the CRC code section.

Abstract: A boundary configuration (Common Input/output CIO) for Generalized Scan Designs (GSD) in a single clock chip design includes at least one generalized scan design internal latch; a boundary scan clock input to the internal latch; an input/output cell connected to the internal latch; and at least one control line between the internal latch and the input/output cell. The CIO GSD is arranged and configured to operate in various modes including a function mode, a RUNBIST/INTEST/LBIST mode, an EXTEST/WIRETEST mode, a SAMPLE/PRELOAD mode, etc. In a different version, a MUX controller is connected to the internal latch. The MUX controller selects data from one of at least two control lines and sending the selected data to at least one internal logic unit of the chip for a test operation.

Abstract: Disclosed is an error detection and correction device for extending error correction time on a data sector beyond the time to receive a next data sector. The error detection and correction device is coupled to sequentially receive a plurality data sectors from a data storage medium. The device includes a buffer and error detection and correction circuitry. The buffer is configured to sequentially receive and store the plurality of data sectors from the data storage medium. The error detection and correction circuitry is configured to sequentially receive the data sectors for sequentially detecting errors in each of the received data sectors. The error detection and correction circuitry corrects the detected errors in the associated sector that is stored in the buffer beyond the time to receive a next data sector in sequence.

Abstract: An apparatus and method are provided for testing component tolerances of a device for testing integrated circuits. The testing device is generally characterized by a plurality of test connectors disposed at a test head, wherein each test connector carries electrical signals for a test channel. Further, each test channel generally corresponds to a circuit board that includes at least one driver and one receiver. In this general type of tester, a system is provided that includes a specialized DUT board that establishes a low impedance electrical connection (i.e., short) between electrical conductors of a first and second test connector. Through this low impedance path, a first driver from a first circuit board is directly connected (i.e., shorted) to a first receiver on a second circuit board. A controller is configured to control the first driver to output an electrical signal at a predetermined time.

Abstract: Disclosed is a Chien search circuit for determining roots to an error locator polynomial that is defined by a set of coefficients. The circuit includes N sub-Chien search circuits, each of which is configured to sequentially evaluate a subset of field elements from a specified set of field elements. Each sub-Chien search circuit includes a set of storage elements, a set of constant multipliers, an adder, and a comparator. The set of storage elements stores a set of values, and receives and stores the set of coefficients as the set of values. One storage element is associated with each coefficient. The set of constant multipliers is coupled to receive the set of values from the set of storage elements. One constant multiplier is associated with one storage element. Each of the constant multipliers is associated with a constant field element and is configured to multiply the received value and the constant field element to generate a product.

Abstract: The invention comprises a method and apparatus for decoding an incoming symbol stream comprised of a plurality of known missing symbols. Within the incoming symbol stream, those symbols corresponding the known missing symbols are replaced with a first set of values to create a modified symbol stream. The modified symbol stream is convolutionally decoded to produce a first decoded information bit stream. An error detection mechanism is performed on the first decoded information bit stream to determine a “pass” or “fail” indication. If the error detection mechanism produces a “fail” indication, a second set of values replaces the known missing symbols to produce a second modified symbol stream. The second modified symbol stream is convolutionally decoded to produce a second decoded information bit stream. The error detection mechanism is performed on the second decoded information bit stream.

Abstract: A source sequence of symbols is communicated over a communications medium by encoding the source sequence according to respective first and second error correction codes to produce respective first and second encoded sequences of symbols. The first and second encoded sequences are processed to produce a communications signal, which is then communicated over the communications medium. The communicated communications signal is processed to produce first and second received sequences of symbols corresponding to the first and second encoded sequences, respectively. The first and second received sequences are selectively recursively decoded according to the associated error correction codes augmented by previous estimates of a symbol of the source sequence to repeatedly produce revised estimates of the symbol until an estimate satisfying a predetermined reliability criteria is obtained.

Abstract: Apparatus, and an associated method, facilitates the efficient utilization of a channel extending between a sending and a receiving station of a digital communication system. A block of symbols to be transmitted by the sending to the receiving station is encoded utilizing a parallel-concatenated encoding technique. Selected encoded versions, or portions thereof, are transmitted by the sending station to the receiving station. The receiving station decodes the signals received thereat. If recovery of the informational content of the block of symbols cannot be effectuated, a request is made to transmit additional encoded versions, or portions thereof, of the block of symbols.

Abstract: A burn-in testing system for evaluating a circuit under test, the system including a burn-in board having a plurality of receptacles, at least one of which being sized to receive the circuit under test, test interface circuitry supported by the board and coupled to the receptacles, the test interface circuitry including a transmitter and receiver; power conductors supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing, control and data signal conductors, a burn-in oven having a compartment selectively receiving the burn-in board and being configured to apply heat within the compartment, and an interrogator unit supported by the burn-in oven, the interrogator unit being configured to send commands to the test interface circuitry to exercise the circuit under test optically or via radio communication and to receive responses to the commands optically or via radio communication.

Abstract: A broadband data interface and a broadband digital interface couples broadband systems to digital client systems. The broadband digital interface is coupled to the digital client systems to transfer data to and from the digital client systems. The broadband digital interface is owned and controlled by the digital client systems. The broadband data interface interfaces broadband systems to the broadband digital interface. The broadband data interface is customized for the particular broadband system such that the broadband data interface is owned and controlled by the operator of the broadband system. The broadband data interface contains a broadband receiver and network access control to permit the broadband system operator to implement access control for data transmitted from the broadband system to the clients.

Abstract: Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.

Abstract: The present invention, generally speaking, takes advantage of the foregoing capability to determine and display the X,Y location corresponding to a net name, by translating functional test data of a digital logic chip passed through a simulation model which identifies one or more defective nets of the chip. The defective nets are processed against a database of the foregoing type to obtain X,Y coordinate data for these nets, allowing them to be data logged as physical traces on the chip layout. In accordance with an exemplary embodiment, this mapping is performed by taking the output from a functional tester and translating it from a list of failed scan chains into a list of suspected netlist nodes. The X,Y coordinates of suspected netlist nodes are then identified and stored in a database, providing failure analysis and yield enhancement engineers a starting point for performing failure analysis and for immediately understanding whether “in-line” inspection data can account for a given failure.

Abstract: A circuit is disclosed that includes a latch circuit and boundary scan cell circuitry. The latch circuit includes a slave latch and a master latch having a data output. The slave latch includes at least a first data input connected to the data output of the master latch, a second data input, and a control input that receives a control signal that controls latching of data present at the second data input. The boundary scan cell circuitry is connected to the second data input and to the control input of the slave latch so that the boundary scan cell circuitry can supply the control signal and data to the slave latch. In one embodiment, the boundary scan cell circuitry is IEEE1149.1-compliant and the circuit further includes either an output driver coupled to the data output of the slave latch or an input receiver coupled to a data input of the master latch.

Abstract: An apparatus for detecting data within a signal having both data and noise is disclosed herein. The apparatus includes means for receiving first samples of an input signal, a first detection unit and a second detection unit. The first detection unit processes the first data samples to create a first bit signal, a second bit signal and a probability related signal. The second detection unit includes first and second modification units and a selection unit. The first and second modification units separately modify the first data samples based on the first and second bit signals, respectively, to create first and second error signals, respectively. The selection unit selects one of the first and second bit signals based on the first and second error signals and a threshold signal.