Abstract: Memory test hardware is provided for generating signals for testing a first memory array and a second memory array. The first memory array and the second memory array may be any two of main memory array, a spare memory array, and reconfiguration memory array, or the apparatus may be adapted for testing all three memory arrays. The memory test hardware may include a controller for generating control signals, a data generator coupled to the controller for generating data signals, and an address generator coupled to the controller for generating address signals. The test device may further include an output data evaluator and repair unit for receiving signals from the main memory array and the spare memory array and for detecting faults in those arrays.

Abstract: A method of locating faults occurred in an LSI (Large Scale Integrated Circuit) is disclosed. Block-by-block logic information each varying in accordance with a test vector are output by dump processing using logic simulation on the basis of circuit connection information. The block-by-block logic information varying in accordance with the test vector are combined with Iddq information showing whether or not an Iddq error has occurred test vector by test vector. These information are used to execute calculation with each block on a test vector basis. As a result, a block involving a fault is detected. Subsequently, a fault is located in the fault block on a transistor basis by use of logic information showing whether or not the Iddq error is present in the block.

Abstract: A method and apparatus for improving the speed and quality of end-to-end data or real-time media transmissions over an internet is disclosed. A media stream being transmitted to the internet is channel coded at the edge of the internet in order to free upstream bit rate for use in source coding the media. The channel coded media stream may then be decoded at a remote edge of the internet to recover lost packets.

Abstract: A method for encoding a digital communication channel is disclosed. The method includes the steps of first storing a frame data, which is inputted for a channel encoding operation, into an encoder RAM (ERAM0); second addressing the ERAM and storing the data into a register via a multiplexer in accordance with a control of a frame selection signal; third addressing the ERAM for reading the previous input data and storing the read data into the register; fourth selecting an input data among two register output data, inputting the selected input data into the convolutional encoder and generating a code symbol; and fifth selecting one among the code symbols and obtaining an output of the channel encoder that completed the convolutional encoding and interleaving operations.

Abstract: A method and device for identifying the manufacturer make and model type of a computer involves scanning the BIOS area of memory for personal computer (PC) configuration data. This scanned data is then used to generate a character-based computer identification string that is unique to a certain type of computer. This string is then compared to a set of known strings to determine the manufacturer make and model type of the polled computer. From scanning a number of personal computers and through user feedback, the process may build upon its knowledge base of personal computers.

Abstract: A method and software apparatus are provided for implementing a dynamically modifiable test flow for integrated circuit devices that adapts to the characteristics of each processed device lot. According to the method of the invention, a modified set of tests sufficient to ensure proper device function for a particular lot is performed, reducing test costs and increasing test capacity. The method and system of the invention periodically samples a predetermined sample number of devices using a full set of tests including a set of skippable tests. Depending upon the performance characteristics of the sample device group on the skippable tests, a number of skippable tests are skipped during a modified test flow. After a next set of devices is tested using the modified test flow, the full set of tests is again performed on another sample group, and the size and makeup of the modified test flow is adjusted according to the new results.

Abstract: An encoder and decoder for generating and decoding convolutional codes of improved orthogonality. In an exemplary embodiment the encoder includes a K-bit length shift register for receiving an input serial stream of information bits and providing for each input bit a K-bit parallel output to a self-doubly orthogonal code sequence generator. The encoded symbol stream is threshold decoded iteratively using the inversion of the convolutional self-doubly orthogonal parity code generators.

Abstract: A memory-test-mode detection circuit for an integrated circuit uses one or more of the input pins of an integrated circuit to detect at least one non-standard signal level. To avoid false triggering several other non-standard logic levels can also be used with some of the other input pins. Each of the non-standard signal levels are detected by a separate signal level detection circuit. A predetermined combination of input signals then provides a control signal which sets the integrated-circuit into a predetermined test mode. A non-standard Vcc/2 signal level is detected by determining that it is above a predetermined low threshold level of 1/4 Vcc and below a predetermined high threshold level of 3/4 Vcc. Additional non-standard input signal levels which are close to Vcc and Vss are also used. A chip enable (CEX) signal is used to enable the signal level detection circuit when a chip is enabled.

Abstract: A computer system includes system memory, containing BIOS instructions, having multiple bootable partitions and the ability to enable Automatic System Recovery (ASR) protection during an early phase of the boot process. Early ASR allows errors occurring during the boot process to be handled by established ASR techniques. Multiple BIOS partitions allows a user to upgrade and/or test new system routines without the potential of losing the functionality of their existing system.

Abstract: A method and an apparatus for automatically inputting debugging data of a video cassette recorder are disclosed. Data generating section reads a debugging data in response to a debugging execution signal from a user and serially generates the read debugging data. Data transmission port outputs the debugging data serially inputted from the data generating section. Data transmission section converts a voltage level and a data form of the debugging data from the data transmission port and transmits the converted debugging data to a video cassette recorder. As a result, an operator can obtain an accurate result of the debugging operation and can easily finish the operation which inputs the debugging data to the video cassette recorder in a small amount of time as well.

Abstract: A method and apparatus for reducing the time for determining a memory refresh frequency for a dynamic random access memory. The method includes disabling the bootstrap circuitry associated with a word line when writing data into a memory cell during a test operation. For instances in which data representing a high logic level is written into the memory cell, the resulting charge that is stored is less than the stored charge under normal operation of the dynamic memory. Consequently, the decay time for the stored charge is shortened, thereby shortening the time for testing the refresh frequency of the memory cell. Testing time for the dynamic memory is thus reduced.

Abstract: An embedded DRAM is incorporated inside a digital-versatile-disk (DVD) playback-controller integrated circuit. Data from the DVD optical disk is written to a data block in the embedded DRAM. Error correction is performed by reading the data block to generate syndromes and over-writing errors in the data block with corrections. Once the data block is corrected, it is copied or moved to a different area of the embedded memory, a host-buffer area. As the data block is moved, de-scrambling is performed to decrypt the data. The re-ordered data is stripped of overhead such as ECC bytes and written to the host-buffer area of the embedded DRAM. A checksum is generated as the data is moved, and the checksum is compared to a stored checksum to ensure that all errors were corrected. The data block in the host-buffer area is then transferred to a host. The embedded DRAM has a very wide data-access width of 16 bytes.

Abstract: An automatic self-testing system includes a plurality of sensor processing channels or paths each having a sensor for providing, either directly or indirectly, a digital value to a comparator which compares the measured value with predetermined value that is, in turn, provided to coincidence logic that evaluates the output of its comparator with the output of the comparators of the other paths to provide an output indicative of a pass/fail condition. Each sensor processing path includes two sub-paths that can be associated with or switched into the processing path while the disassociated sub-path undergoes off-line testing by a test processor. Testing is effected by providing a digital value to the sub-path under test while sensing the output to determine the functional validity of the sub-path under test. The combinational logic state of the system is monitored and converted into a decimal value that is compared with the set of decimal values corresponding to the finite known-good logic states of the system.

Abstract: A digital data recording channel which uses variable rate encoding. The encoder monitors an input bit stream for sequences associated with selected readback characteristics, and inserts one or more bits where desirable to improve the characteristics of the stored bit stream.

Abstract: A data error correcting method and apparatus reads two dimensional block data having row data and row error correcting codes and column data and column error correcting codes. In the block data, one column error correcting code is assigned to one column data group, and individual column data groups and individual column error correcting codes are alternately arranged. A control unit corrects errors in the block data on a row by row basis using the row error correcting codes and the row data. The control unit also corrects errors on a column by column basis, in parallel with the row errors, using the column error correcting codes and the column data. The control unit includes a compensation input data generator having a data adjustor and a Galois multiplier. The data adjustor computes a Compensation Galois constant for compensating the input order of the data.

Abstract: A method of testing a memory device having two arrays of memory cells arranged in rows and columns. Sense amplifiers for respective columns are shared by the arrays, with the sense amplifiers being selectively coupled to the digit lines of respective columns in each array by respective isolation transistors. Cells of the memory array are tested by first writing known data bits to each of the cells. The isolation transistors for the first array are then turned on, and the isolation transistors for the second array are turned off. Predetermined voltages are coupled to the sense amplifiers through the digit lines of the first array by activating a row in the first array. A plurality of rows in the first array are then activated to couple the memory cells in each activated row to respective digit lines. The sense amplifiers are then coupled to respective digit lines in the second array by turning on the isolation transistors for the second array.

Abstract: An encoded message, includes a plurality of data items and a plurality of redundant data items. Each of the plurality of redundant data items corresponds to a number of the data items, with respective redundant data items corresponding to different numbers of data items.

Abstract: A test circuit in a memory device includes test data read paths and test data write paths for performing data compression to more quickly test the memory cells in the memory device. The memory device includes first and second banks of memory cells having a redundancy plane defined between the two banks and including at least one data terminal. The test circuit includes a test mode terminal adapted to receive a test mode signal, and a test data write path coupled to a plurality of memory cells in the first and second banks. The test circuit further includes a first test data read path coupled to a plurality of memory cells in the first bank, and a second test data read path coupled to a plurality of memory cells in the second bank. A test data write circuit is coupled to the data terminal and to the test data write path and transfers test data placed on the data terminal over the test data write path to a plurality of memory cells in the first and second banks.

Abstract: A BIST circuit for use with a read channel device is disclosed that utilizes internally generated clock and control signals to control a test sequence. A linear feedback shift register is used as the signature analysis register. The test signature accumulation process is controlled by clock and control signals internal to the read charnel device that are associated with the normal operation of the read channel device.

Abstract: A system and method for recovering lost/damaged attribute data in a bitstream of encoded data comprising attribute data and encoded sample data is disclosed. The decoded neighboring data is retrieved and lost/damaged attribute data is estimated using the encoded sample data, the decoded neighboring data, and available attribute data. In one embodiment, this is used in the transmission of video signals over a potentially lossy communications channel.