Abstract: A heat dissipation sheet includes a first sheet composed of a plurality of first carbon nanotubes, and a second sheet composed of a plurality of second carbon nanotubes, wherein the first sheet and the second sheet are coupled in a stacked state, and the first carbon nanotubes and the second carbon nanotubes are different in an amount of deformation when pressure is applied.

Abstract: An integrated circuit includes a first-type active-region structure, a second-type active-region structure on a substrate, and a plurality of gate-conductors. The integrated circuit also includes a backside horizontal conducting line in a backside first conducting layer below the substrate, a backside vertical conducting line in a backside second conducting layer below the backside first conducting layer, and a pin-connector for a circuit cell. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across a vertical boundary of the circuit cell.

Abstract: An integrated circuit includes a set of power rails on a back-side of a substrate, a first flip-flop, a second flip-flop and a third flip-flop. The set of power rails extend in a first direction. The first flip-flop includes a first set of conductive structures extending in the first direction. The second flip-flop abuts the first flip-flop at a first boundary, and includes a second set of conductive structures extending in the first direction. The third flip-flop abuts the second flip-flop at a second boundary, and includes a third set of conductive structures extending in the first direction. The first, second and third flip-flop are on a first metal layer and are on a front-side of the substrate opposite from the back-side. The second set of conductive structures are offset from the first boundary and the second boundary in a second direction.

Abstract: A semiconductor image sensor includes a pixel. The pixel includes a first substrate; and a photodiode in the first substrate. The semiconductor image sensor further includes an interconnect structure electrically connected to the pixel. The semiconductor image sensor further includes a reflection structure between the interconnect and the photodiode, wherein the reflection structure is configured to reflect light passing through the photodiode back toward the photodiode.

Abstract: Disclosed is a semiconductor device comprising a substrate, a first lower pattern group on the substrate and including a first key pattern and first lower test patterns horizontally spaced apart from the first key pattern, and a first upper pattern group on the first lower pattern group and including first pads horizontally spaced apart from each other and first upper test patterns between adjacent ones of the first pads. The first key pattern is configured to be used for a photography process associated with fabrication of the semiconductor device. The first pads are electrically connected to the first upper test patterns. One of the first pads vertically overlaps with the first key pattern.

Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.

Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.

Abstract: The present disclosure provides a semiconductor structure, including a substrate including a first material, wherein the first material generates electrical signals from radiation within a first range of wavelengths, an image sensor element including a second material, wherein the second material generates electrical signals from radiation within a second range of wavelengths, the second range is different from first range, a transparent layer proximal to a light receiving surface of the image sensor element, wherein the transparent layer is transparent to radiation within the second range of wavelength, and an interconnect structure connected to a signal transmitting surface of the image sensor element.

Abstract: A method of forming an insulation structure inside and on top of a first semiconductor substrate, including the steps of: a) forming a trench vertically extending in the first substrate from a first surface of the first substrate; b) filling the trench, from the first surface of the first substrate, with a polysilicon region; c) thinning the first substrate on the side of a second surface of the first substrate, opposite to the first surface, to expose the polysilicon region at the bottom of the trench; d) removing the polysilicon region from the second surface of the first substrate; and e) filling the trench, from the second surface of the first substrate, with a metal.

Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer; an insulating layer; a first region disposed between the nitride semiconductor layer and the insulating layer and containing at least one element of hydrogen and deuterium; and a second region disposed in the nitride semiconductor layer, adjacent to the first region, and containing fluorine.

Abstract: A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.

Abstract: Apparatus and methods to control the phase of power sources for plasma process regions in a batch process chamber. A master exciter controls the phase of the power sources during the process sequence based on feedback from the match circuits of the respective plasma sources.

Abstract: Embodiments of a Majorana-based qubit are disclosed herein. The qubit is based on the formation of superconducting islands, some parts of which are topological (T) and some parts of which are non-topological. Also disclosed are example techniques for fabricating such qubits. In one embodiment, a semiconductor nanowire is grown, the semiconductor nanowire having a surface with an oxide layer. A dielectric insulator layer is deposited onto a portion of the oxide layer of the semiconductor nanowire, the portion being designed to operate as a non-topological segment in the quantum device. An etching process is performed on the oxide layer of the semiconductor nanowire that removes the oxide layer at the surface of the semiconductor nanowire but maintains the oxide layer in the portion having the deposited dielectric insulator layer. A superconductive layer is deposited on the surface of the semiconductor nanowire, including over the dielectric insulator layer.

Abstract: A sensor device includes: a semiconductor substrate having a sensing region which extends vertically below a main surface region of the semiconductor substrate into the substrate; a semiconductor capping layer that extends vertically below the main surface region into the substrate; a buried deep trench structure that extends vertically below the capping layer into the substrate and laterally relative to the sensing region, the buried deep trench structure including a doped semiconductor layer that extends from a surface region of the buried deep trench structure into the substrate; a trench doping region that extends from the doped semiconductor layer of the buried deep trench structure into the substrate; and electronic circuitry for the sensing region in a capping region of the substrate vertically above the buried deep trench structure. Methods of manufacturing the sensor device are also provided.

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

Abstract: An image sensor is fabricated by first heavily p-type doping the thin top monocrystalline silicon substrate of an SOI wafer, then forming a relatively lightly p-doped epitaxial layer on a top surface of the top silicon substrate, where p-type doping levels during these two processes are controlled to produce a p-type dopant concentration gradient in the top silicon substrate. Sensing (circuit) elements and associated metal interconnects are fabricated on the epitaxial layer, then the handling substrate and oxide layer of the SOI wafer are at least partially removed to expose a lower surface of either the top silicon substrate or the epitaxial layer, and then a pure boron layer is formed on the exposed lower surface. The p-type dopant concentration gradient monotonically decreases from a maximum level near the top-silicon/epitaxial-layer interface to a minimum concentration level at the epitaxial layer's upper surface.

Abstract: Wafer-level packaging of solid-state transducers (“SSTs”) is disclosed herein. A method in accordance with a particular embodiment includes forming a transducer structure having a first surface and a second surface opposite the first surface, and forming a plurality of separators that extend from at least the first surface of the transducer structure to beyond the second surface. The separators can demarcate lateral dimensions of individual SSTs. The method can further include forming a support substrate on the first surface of the transducer structure, and forming a plurality of discrete optical elements on the second surface of the transducer structure. The separators can form barriers between the discrete optical elements. The method can still further include dicing the SSTs along the separators. Associated SST devices and systems are also disclosed herein.

Abstract: A light emitting device having first, second and third dimensions that are orthogonal may include a light emitting semiconductor device configured to emit light via a first surface in a plane formed by the first and second dimensions. The light emitting device may further include a wavelength converting structure disposed on the first surface of the light emitting semiconductor device, the wavelength converting structure extending beyond the light emitting semiconductor device in the first dimension and the light emitting semiconductor device extending beyond the wavelength converting structure in the second dimension. The light emitting device may further include one or more optical extraction features in at least one gap formed by the wavelength converting structure extending beyond the light emitting semiconductor structure in the first dimension and/or formed by the light emitting semiconductor structure extending beyond the wavelength converting structure in the second dimension.

Abstract: For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.