Abstract: A shielding element comprises a rigid substrate and at least one electrically conductive two-dimensional structure which is placed on one of the faces of the substrate. The substrate and the electrically conductive two-dimensional structure are such that the shielding element has optical-transmission and shielding-efficiency values at least one of which varies between two zones of the shielding element. Such a shielding element enables easier assembly of a detection system comprising multiple optical sensors.

Abstract: A bonding apparatus for bonding a driving circuit to a display panel includes: a bonding stage unit on which the display panel is supported in bonding the driving circuit to the display panel; a head unit located above the bonding stage unit and with which ultrasonic waves are applied to the driving circuit to couple the driving circuit with a bonding area of the display panel supported on the bonding stage unit; and a protrusion disposed at an edge portion of the bonding stage unit, the edge portion corresponding to an end of the display panel at which the bonding area is disposed.

Abstract: A MOSFET includes a semiconductor body having a first side, a drift region, a body region forming a first pn-junction with the drift region, a source region forming a second pn-junction with the body region, in a vertical cross-section, a dielectric structure on the first side and having an upper side; a first gate electrode, a second gate electrode, a contact trench between the first and second gate electrodes, extending through the dielectric structure to the source region, in a horizontal direction a width of the contact trench has, in a first plane, a first value, and, in a second plane, a second value which is at most about 2.5 times the first value, and a first contact structure arranged on the dielectric structure having a through contact portion arranged in the contact trench, and in Ohmic contact with the source region.

Abstract: A system in package includes a memory-die stack in memory module that is stacked vertically with respect to a processor die. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. Some configurations include the vertical bond wire emerging orthogonally beginning from a bond-wire pad. The matrix encloses the memory-die stack, the spacer, and at least a portion of the processor die.

Abstract: Provided is a film for manufacturing a semiconductor part in which an evaluation step accompanied with a temperature change, a segmenting step, and a pickup step can be commonly performed, a method for manufacturing a semiconductor part, a semiconductor part, and an evaluation method. The film includes a base layer, and an adhesive layer disposed on one surface side of the base layer, wherein the ratio RE (=E?(160)/E?(?40)) of the elastic modulus of the base layer at 160° C. to the elastic modulus of the base layer at ?40° C. is RE?0.01, and the elastic modulus E?(?40) is 10 MPa to less than 1000 MPa. The method includes bonding the adhesive layer to a back surface of a semiconductor wafer, separating the semiconductor wafer into segments to obtain semiconductor parts, and separating the semiconductor parts from the adhesive layer, and includes a step of evaluating.

Abstract: Emergency stop pressure sensors 17 are installed on both side surfaces of a movable link 11 of a robot arm 14 of an assembly robot. When a worker S unintentionally walks in a swing range Ra of the robot arm 14 and contacts the emergency stop pressure sensor 17, a detection signal is transmitted to a control unit 19, and the control unit 19 shuts power transmission to a driving source swinging the robot arm. The emergency stop pressure sensor 17 has a first electrode and a second electrode constituting a pair of electrodes and an intermediate layer formed of rubber or a rubber composition, which is disposed between the pair of electrodes, the intermediate layer generating power upon deformation caused by contact with a contacted body (the worker). A side of the intermediate layer in a laminate direction undergoes surface modification treatment and/or inactivation treatment.

Abstract: A semiconductor package structure including a sensor die, a substrate, a light blocking layer, a circuit layer, a dam structure and an underfill is provided. The sensor die has a sensing surface. The sensing surface includes an image sensing area and a plurality of conductive bumps. The substrate is disposed on the sensing surface. The light blocking layer is located between the substrate and the sensor die. The circuit layer is disposed on the light blocking layer. The sensor die is electrically connected to the circuit layer by the conductive bumps. The dam structure is disposed on the substrate and surrounds the image sensing area. Opposite ends of the dam structure directly contact the sensor die and the light blocking layer. The underfill is disposed between the dam structure and the conductive bumps.

Abstract: The disclosure discloses a method for forming a doped epitaxial layer of contact image sensor. Epitaxial growth is performed in times. After each time of epitaxial growth, trench isolation and ion implantation are performed to form deep and shallow trench isolation running through a large-thickness doped epitaxial layer. Through cyclic operation of epitaxial growth, trench isolation and ion implantation, the photoresist and hard mask required at each time do not need to be too thick. In the process of trench isolation and ion implantation, the photoresist and etching morphologies are good, such that the lag problem of the prepared contact image sensor is improved. By forming the large-thickness doped epitaxial layer by adopting the method for forming the doped epitaxial layer of the contact image sensor, a high-performance contact image sensor applicable to high quantum efficiency, small pixel size and near infrared/infrared can be prepared.

Abstract: A method for forming reliefs on a face of a substrate is provided, successively including forming a protective screen for protecting at least a first zone of the face; an implanting to introduce at least one species comprising carbon into the substrate from the face of the substrate, the forming of the protective screen and the implanting being configured to form, in the substrate, at least one carbon modified layer having a concentration of implanted carbon greater than or equal to an etching threshold only from a second zone of the face of the substrate not protected by the protective screen; removing the protective screen; and etching the substrate from the first zone selectively with respect to the second zone.

Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.

Abstract: A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.

Abstract: Transistors might include first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.

Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

Abstract: The method of the present invention improves mechanical integrity of a crystalline silicon solar cell having an exposed layer of n-type silicon. A solution of electrically-conductive nanowires in an inert liquid is sprayed onto the exposed layer in order to form a grid pattern of the nanowires on the exposed layer after the inert liquid dries or evaporates.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes performing a first process of forming a concave portion in the first film and forming a second film on a surface of the first film that is exposed in the concave portion by using a first gas containing a carbon element and a fluorine element. The method further includes performing a second process of exposing the second film to a second gas containing a hydrogen element or a fluid generated from the second gas.

Abstract: A substrate processing apparatus, including: a development part configured to develop a substrate on which an exposed resist film formed to form a pattern on a surface of the substrate; a heat plate configured to mount and heat the substrate on which the resist film formed on the heat plate before the development is performed; a distribution acquisition part configured to optically acquire a size distribution of a dimension of the pattern on the surface of the substrate; and a determination part configured to determine whether abnormality has occurred in a mounting state of the substrate on the heat plate, based on the size distribution of the dimension of the pattern.

Abstract: A wafer-level process includes providing a set of electronic chips, including a stack with a set of matrix arrays of pixels, an interconnect layer electrically connected to the set of matrix arrays of pixels, and a first layer, including vias electrically connected to the interconnect layer. The wafer-level process further includes forming metal pillars on the first layer, the pillars being electrically connected to the vias, and forming a material integrally with the first layer, around the metal pillars. The wafer-level process also includes dicing the electronic chips so as to release the thermomechanical stresses to which the stack is subjected. Finally, the wafer-level process includes making the metal pillars coplanar after dicing the electronic chips.

Abstract: To realize miniaturization of a pixel, reduction in noise, and high quantum efficiency, and to improve short-wavelength sensitivity while suppressing inter-pixel interference and variations for each pixel. According to the present disclosure, there is provided an imaging device including: a first semiconductor layer formed in a semiconductor substrate; a second semiconductor layer of a conductivity type opposite to a conductivity type of the first semiconductor layer formed on the first semiconductor layer; a pixel separation unit which defines a pixel region including the first semiconductor layer and the second semiconductor layer; a first electrode which is connected to the first semiconductor layer from one surface side of the semiconductor substrate; and a second electrode which is connected to the second semiconductor layer from a light irradiation surface side that is the other surface of the semiconductor substrate, and is formed to correspond to a position of the pixel separation unit.

Abstract: A fabrication method includes arranging a plurality of dice on a substrate and performing a first etching process that etches a first layer of the substrate at a boundary between adjacent dice on the substrate. The etching forms facets of one or more waveguides that are defined within the first layer, and the etching leaves a portion of the first layer in the boundary between the adjacent dice. The method continues with a second etching process that etches the portion of the first layer and a second layer beneath the portion of the first layer, the second etching process forming a trench in the boundary where the second layer has a different material than the first layer. The method also includes separating the dice from one another along the trench.

Abstract: The present invention discloses a semiconductor-on-diamond-on-carrier substrate wafer. The semiconductor-on-diamond-on-carrier wafer comprises: a semiconductor-on-diamond wafer having a diamond side and semiconductor side; a carrier substrate disposed on the diamond side of the semiconductor-on-diamond wafer and including at least one layer having a lower coefficient of thermal expansion (CTE) than diamond; and an adhesive layer disposed between the diamond side of the semiconductor-on-diamond wafer and the carrier substrate to bond the carrier substrate to the semiconductor-on-diamond wafer. The semiconductor-on-diamond-on-carrier substrate wafer has the following characteristics: a total thickness variation of no more than 40 ?m; a wafer bow of no more than 100 ?m; and a wafer warp of no more than 40 ?m.