Abstract: A method making it possible to obtain, on an upper surface of a crystalline substrate, a semipolar layer of nitride material comprising any one from among gallium, aluminium or indium, the method comprises the following steps: obtaining, on the upper surface of the crystalline substrate, a plurality of parallel grooves which extend in a first direction, one of the two opposite facets exhibiting a crystal orientation; etching a plurality of parallel slices which extend in a second direction that has undergone a rotation with respect to the first direction of the grooves in such a way as to obtain individual facets exhibiting a crystal orientation; epitaxial growth of the material from the individual facets.

Abstract: A patch on interposer (PoINT) package is described with a wireless communications interface. Some examples include an interposer, a main patch attached to the interposer, a main integrated circuit die attached to the patch, a second patch attached to the interposer, and a millimeter wave radio die attached to the second patch and coupled to the main integrated circuit die through the interposer to communicate data between the main die and an external component.

Abstract: A film deposition apparatus includes a process chamber and a turntable provided in the process chamber. The turntable includes a substrate receiving region to receive a substrate thereon and provided along a circumferential direction of the turntable. A source gas supply unit extending along a radial direction of the turntable is provided above the turntable with a first distance from the turntable such that the source gas supply unit covers an entire length of the substrate receiving region in the radial direction. An axial-side supplementary gas supply unit is provided in the vicinity of the source gas supply unit and above the turntable with a second distance from the turntable. The second distance is longer than the first distance. The axial-side supplementary gas supply unit covers a predetermined region of the substrate receiving region on the axial side in the radial direction of the turntable.

Abstract: An etching method includes providing a plasma of a first treatment gas to an etching-object to form a deposition layer on the etching-object, the first treatment gas including a fluorocarbon gas and an inert gas, and the etching-object including a first region including silicon oxide and a second region including silicon nitride, providing a plasma of an inert gas to the etching-object having the deposition layer thereon to activate an etching reaction of the silicon oxide, wherein a negative direct current voltage is applied to an opposing part that is spaced apart from the etching-object so as to face an etching surface of the etching-object, the opposing part including silicon, and subsequently, providing a plasma of a second treatment gas to remove an etching reaction product, the second treatment gas including an inert gas and an oxygen-containing gas.

Abstract: Wafer-level packaging of solid-state transducers (“SSTs”) is disclosed herein. A method in accordance with a particular embodiment includes forming a transducer structure having a first surface and a second surface opposite the first surface, and forming a plurality of separators that extend from at least the first surface of the transducer structure to beyond the second surface. The separators can demarcate lateral dimensions of individual SSTs. The method can further include forming a support substrate on the first surface of the transducer structure, and forming a plurality of discrete optical elements on the second surface of the transducer structure. The separators can form barriers between the discrete optical elements. The method can still further include dicing the SSTs along the separators. Associated SST devices and systems are also disclosed herein.

Abstract: Embodiments of a Majorana-based qubit are disclosed herein. The qubit is based on the formation of superconducting islands, some parts of which are topological (T) and some parts of which are non-topological. Also disclosed are example techniques for fabricating such qubits. In one embodiment, a semiconductor nanowire is grown, the semiconductor nanowire having a surface with an oxide layer. A dielectric insulator layer is deposited onto a portion of the oxide layer of the semiconductor nanowire, the portion being designed to operate as a non-topological segment in the quantum device. An etching process is performed on the oxide layer of the semiconductor nanowire that removes the oxide layer at the surface of the semiconductor nanowire but maintains the oxide layer in the portion having the deposited dielectric insulator layer. A superconductive layer is deposited on the surface of the semiconductor nanowire, including over the dielectric insulator layer.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stack comprising a plurality of conductive layers stacked one over the other in a first direction, and an insulating layer interposed between adjacent conductive layers located over the substrate, a first semiconductor layer extending inwardly of the stack and through the plurality of conductive layers in the first direction, a memory layer located between the first semiconductor layer and the plurality of conductive layers, and a second semiconductor layer located over, and in contact with, the first semiconductor layer, wherein the second semiconductor layer includes a third semiconductor layer containing phosphorous, and a fourth semiconductor layer containing carbon provided between the first semiconductor layer and the third semiconductor layer.

Abstract: A method and apparatus for material deposition onto a sample to form a protective layer composed of at least two materials that have been formulated and arranged according to the material properties of the sample.

Abstract: A method is provided. First and second fins are etched to form a first recess over the etched first fin and a second recess over the etched second fin. A first composite fin and a second composite fin are concurrently epitaxially grown respectively in the first recess and the second recess. The first composite fin includes a plurality of nanowire channels and at least one sacrificial layer. The second composite fin includes at least one nanowire channel and at least one sacrificial layer. A number of the plurality of nanowire channels of the first composite fin is greater than a number of the at least one nanowire channel of the second composite fin. A dielectric material is recessed to expose at least a portion of the first composite fin and at least a portion of the second composite fin.

Abstract: Fabrication of a circuit with superposed transistors includes assembly of a structure having transistors formed from a first semiconducting layer with a support provided with a second semiconducting layer in which transistors are provided on a higher level. The second semiconducting layer is coated with a thin layer of silicon oxide. The assembly of said structure and the support is made by direct bonding in which the thin silicon oxide layer is bonded to oxidised portions of getter material.

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate, generally extending along a first horizontal direction, and laterally spaced apart from each other along a second horizontal direction by width-modulated line trenches, memory films located on a respective sidewall of the alternating stacks, the memory films containing a charge storage layer and blocking dielectric which generally extend along the first horizontal direction and laterally undulate along the second horizontal direction, and a plurality of discrete vertical semiconductor channels located on a sidewall of a respective one of the memory films.

Abstract: A magnetic memory device includes a magnetic memory stack including a bottom electrode and having a hard mask formed thereon. An encapsulation layer is formed over sides of the magnetic memory stack and has a thickness adjacent to the sides formed on the bottom electrode. A dielectric material is formed over the encapsulation layer and is removed from over the hard mask and gapped apart from the encapsulation layer on the sides of the magnetic memory stack to form trenches between the dielectric material and the encapsulation layer at the sides of the magnetic memory stack. A top electrode is formed over the hard mask and in the trenches such that the top electrode is spaced apart from the bottom electrode by at least the thickness.

Abstract: The present disclosure generally relates to devices having conformal semiconductor cladding materials, and methods of forming the same. The cladding material is a silicon germanium epitaxial material. The cladding material is capable of being deposited to a thickness which is less than cladding materials formed by conventional deposition/etch techniques.

Abstract: Provided is a power module package including: a substrate; at least one electrode arranged on the substrate; and an encapsulation member covering at least a portion of the substrate, the encapsulation member including a housing unit housing the at least one electrode. The at least one electrode is spaced apart from the encapsulation member.

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate, generally extending along a first horizontal direction, and laterally spaced apart from each other along a second horizontal direction by width-modulated line trenches, memory films located on a respective sidewall of the alternating stacks, generally extending along the first horizontal direction, and laterally undulating along the second horizontal direction, and a plurality of discrete vertical semiconductor channels located on a sidewall of a respective one of the memory films.

Abstract: A technique relates to a semiconductor device. One or more N-type field effect transistor (NFET) gates and one or more P-type field effect transistor (PFET) gates are formed. Source and drain (S/D) contacts are formed, at least one material of the S/D contacts being formed in the PFET gates. Insulating material is deposited as self-aligned caps above the NFET gates and the PFET gates, while the insulating material is also formed as insulator portions adjacent to the S/D contacts. Middle of the line (MOL) contacts are formed above the S/D contacts.

Abstract: A method of forming a semiconductor structure includes, in a radio frequency (RF) deposition chamber, depositing a titanium film using physical vapor deposition and forming a graded hard mask film by reactive sputtering the titanium film with nitrogen in the RF deposition chamber. The graded hard mask film is a titanium nitride film with a graded vertical concentration of nitrogen. The method may further include, during deposition of the titanium film and during formation of the graded hard mask film, modulating one or more parameters of the RF deposition chamber, such as modulating an auto capacitance tuner (ACT) current, modulating the RF power, and modulating the pressure of the RF deposition chamber.

Abstract: A substrate to be encapsulated, an encapsulation assembly and a display device are provided. The substrate to be encapsulated comprises a base substrate, and a plurality of notches arranged in an array located in a region to be attached to an encapsulation layer, wherein the plurality of notches have a same shape of regular polygon.

Abstract: A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, an interlayer insulating layer, at least one electrode, an inorganic protective layer, and an organic protective layer. The interlayer insulating layer is formed on the semiconductor substrate and has at least one opening. The at least one electrode has part formed on an edge of the at least one opening, and has other part electrically connected, in the at least one opening, to the semiconductor substrate. The inorganic protective layer includes an inner edge portion and an outer edge portion. The inner edge portion covers an edge of the at least one electrode. The inorganic protective layer, except for the inner edge portion, is formed on the interlayer insulating layer. The organic protective layer covers the inorganic protective layer. One of the inner edge portion and the outer edge portion of the inorganic protective layer has an undercut.

Abstract: A method for fabricating an electronic device including a semiconductor memory may include forming a buffer layer over a substrate, the buffer layer operable to aide in crystal growth of an under layer; forming the under layer over the buffer layer, the under layer operable to aide in crystal growth of a free layer; and forming a Magnetic Tunnel Junction (MTJ) structure including the free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer over the under layer.