Patents Examined by Alexander Oscar Williams
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Patent number: 10158054Abstract: An LED lighting device is disclosed. The LED lighting device uses a violet LED chip as a light source for exciting quantum dots. The quantum dots excited by the light of the violet LED chip are mixed with each other to form white light. So, the LED lighting device not just has the effects of providing a high luminous efficiency and preventing the blue light from damaging human eyes only, but also provides a better color rendering ability.Type: GrantFiled: October 5, 2017Date of Patent: December 18, 2018Assignee: Unity Opto Technology Co., Ltd.Inventors: Wei-Chung Lin, Hung-Li Yeh, Ko-Wei Lu
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Patent number: 10157893Abstract: Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures are provided. A structure may include a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.Type: GrantFiled: October 25, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Mirng-Ji Lii, Chung-Shi Liu, Ming-Da Cheng
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Patent number: 10147718Abstract: An ESD circuit includes a first metal oxide channel device having a drain coupled to a first node, a source coupled to a second node, and a gate coupled to the first node; a second metal oxide channel device having a source coupled to the first node, a drain coupled to the second node, and a gate coupled to the second node; a first capacitor coupled between the first and second nodes proximate to the first metal oxide channel device; and a second capacitor coupled between the first and second nodes proximate to the second metal oxide channel device. The ESD circuit can further include a third capacitor coupled between the first and second nodes proximate to the first capacitor. The ESD circuit can further include a fourth capacitor coupled between the first and second nodes proximate to the second capacitor.Type: GrantFiled: October 23, 2017Date of Patent: December 4, 2018Assignee: DPIX, LLCInventors: Byung-Kyu Park, Karthik Nagarajan, Jungwon Park, Yang-Wen Chen, Ick-Hwan Ko
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Patent number: 10128182Abstract: A semiconductor structure includes a substrate; a die disposed over the substrate, and including a die pad, a conductive via disposed over the die pad and a dielectric material surrounding the conductive via; a molding disposed over the substrate and surrounding the die; a lower dielectric layer disposed nearer the substrate and over the dielectric material and the molding; and an upper dielectric layer disposed further the substrate and over the lower dielectric layer, wherein a material content ratio in the upper dielectric layer is substantially greater than that in the lower dielectric layer, and the material content ratio substantially inversely affects a mechanical strength of the upper dielectric layer and the lower dielectric layer.Type: GrantFiled: January 19, 2017Date of Patent: November 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsi-Kuei Cheng, Chih-Kang Han, Ching-Fu Chang, Hsin-Chieh Huang
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Patent number: 10128217Abstract: Semiconductor devices with controllers under stacks of semiconductor packages and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate, a controller attached to the package substrate, and at least two semiconductor packages disposed over the controller. Each semiconductor package includes a plurality of semiconductor dies. The semiconductor device further includes an encapsulant material encapsulating the controller and the at least two semiconductor packages.Type: GrantFiled: February 13, 2017Date of Patent: November 13, 2018Assignee: Micron Technology, Inc.Inventors: Seng Kim Ye, Hong Wan Ng
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Patent number: 10115651Abstract: An electronic component includes a substrate that has a first principal surface and a second principal surface, a chip that includes a mounting surface on which a plurality of terminal electrodes are formed and a non-mounting surface positioned on a side opposite to the mounting surface and that is arranged at the first principal surface of the substrate in a posture in which the mounting surface faces the first principal surface of the substrate, and a sealing resin that seals the chip at the first principal surface of the substrate so as to expose the non-mounting surface of the chip.Type: GrantFiled: May 1, 2017Date of Patent: October 30, 2018Assignee: ROHM CO., LTD.Inventor: Isamu Nishimura
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Patent number: 10105863Abstract: A method for operating an object detection system in a saw produces profiles for materials used in work pieces. The method includes operating a motor in the saw to move an implement and cut a work piece formed from a predetermined material, recording, a sensing signal produced in the object detection system during contact between the work piece and the implement, generating a detection profile for the material of the work piece based on the recorded sensing signal, storing, the detection profile in a memory in the saw, and operating the saw and the object detection system using the detection profile to distinguish between contact of the implement with a work piece formed from the predetermined material and contact of the implement with a portion of a body of an operator.Type: GrantFiled: March 4, 2016Date of Patent: October 23, 2018Assignees: Robert Bosch Tool Corporation, Robert Bosch GmbHInventors: Bharadwaja Maharshi Ramaswamy, Eric Laliberte
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Patent number: 10109583Abstract: Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.Type: GrantFiled: December 24, 2014Date of Patent: October 23, 2018Assignee: Intel CorporationInventors: Robert L. Bristol, Manish Chandhok, Jasmeet S. Chawla, Florian Gstrein, Eungnak Han, Rami Hourani, Kevin Lin, Richard E. Schenker, Todd R. Younkin
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Patent number: 10109819Abstract: A mirror device has a plurality of organic EL elements and a plurality of metal mirror surface portions that are divided by banks made of a light-transmissive dielectric material and aligned on a substrate. Each of the organic EL elements has an organic layer that is formed between a light-transmissive electrode and a reflection electrode and contains a light-emitting layer. Each of the metal mirror surface portions and each of the organic EL elements or each group of the metal mirror surface portions and each group of the organic EL elements are alternately disposed.Type: GrantFiled: January 20, 2017Date of Patent: October 23, 2018Assignee: PIONEER CORPORATIONInventors: Ayako Yoshida, Kazuo Kuroda
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Patent number: 10090371Abstract: An organic light emitting diode display includes a plurality of pixels. At least one pixel is connected to a scan line receive a scan signal, a data line to receive a data signal, and voltage line to receive a driving voltage. The at least one pixel includes a switching transistor including a switching drain electrode to output the data voltage, a driving transistor including a driving source electrode connected to the switching drain electrode, and an organic light emitting diode connected to a driving drain electrode of the driving transistor. The driving source electrode is separated from the data line.Type: GrantFiled: June 22, 2017Date of Patent: October 2, 2018Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Mi Hae Kim, Min Ho Ko, Seung Woo Sung, Ki Myeong Eom, Jin Jeon
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Patent number: 10090252Abstract: A semiconductor device may include a bottom package embedded with a first semiconductor chip. The semiconductor device may include a middle package stacked over the bottom package, and embedded with at least two second semiconductor chips in a fan-out structure. The semiconductor device may include a top package stacked over the middle package, and embedded with at least two third semiconductor chips.Type: GrantFiled: September 8, 2017Date of Patent: October 2, 2018Assignee: SK hynix Inc.Inventors: Sang Eun Lee, Seung Taek Yang
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Patent number: 10074605Abstract: Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via. A word line is coupled to a row of the array of memory cells.Type: GrantFiled: November 16, 2016Date of Patent: September 11, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Jhon Jhy Liaw
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Patent number: 10074585Abstract: A power module includes a connection terminal for external connection, the connection terminal protruding from the side surface of a package, and a dummy terminal protruding from the side surface of the package and shorter than the connection terminal. The dummy terminal is processed to have a bottom surface with an inclination. In other words, the distance between a plane containing a heat dissipation surface of the package and the dummy terminal increases toward the extremity of the dummy terminal. Accordingly, when a heat dissipation fin is attached to the heat dissipation surface, the extremity of the dummy terminal is more distant from the heat dissipation fin than the rest of the dummy terminal.Type: GrantFiled: January 20, 2015Date of Patent: September 11, 2018Assignee: Mitsubishi Electric CorporationInventors: Shogo Shibata, Maki Hasegawa
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Patent number: 10068879Abstract: An integrated circuit (IC) device is described. The IC device includes a substrate. A connection component including a cavity therethrough is attached to the substrate. A memory die is positioned in the cavity of the connection component and is electrically coupled to the substrate. A logic die extends over the memory die and at least a portion of the connection component, and is electrically coupled to the connection component and the memory die. The connection component is formed free of through silicon vias and is electrically coupled to the substrate through wire bonding.Type: GrantFiled: September 19, 2016Date of Patent: September 4, 2018Assignee: GENERAL ELECTRIC COMPANYInventor: Arun Virupaksha Gowda
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Patent number: 10068868Abstract: A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.Type: GrantFiled: February 15, 2017Date of Patent: September 4, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Liang Shao, Chih-Hang Tung, Wen-Lin Shih, Hsiao-Yun Chen, Chen-Hua Yu
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Patent number: 10062670Abstract: A packaged module for use in a wireless communication device has a substrate supporting a crystal and a first die that includes at least a microprocessor and one or more of radio frequency transmitter circuitry and radio frequency receiver circuitry. The first die is disposed between the crystal and the substrate. An overmold encloses the first die and the crystal. The substrate also supports a second die that includes at least a power amplifier for amplifying a radio frequency input signal, where the second die is disposed on an opposite side of the substrate from the first die and the crystal.Type: GrantFiled: April 17, 2017Date of Patent: August 28, 2018Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Darren Roger Frenette, George Khoury, Leslie Paul Wallis
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Patent number: 10043752Abstract: An integrated circuit device may include a front-side contact coupled to a front-side metallization. The integrated circuit device may further include a backside contact coupled to a backside metallization. The front-side contact may be directly coupled to the backside contact.Type: GrantFiled: August 23, 2016Date of Patent: August 7, 2018Assignee: QUALCOMM IncorporatedInventors: Perry Wyan Lou, Sinan Goktepeli
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Patent number: 10043779Abstract: Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device (“PoP”) with enhanced tolerance for warping. In one such packaged microelectronic device, interconnect structures are in an outer region of the packaged microelectronic device. A microelectronic device is coupled in an inner region of the packaged microelectronic device inside the outer region. A dielectric layer surrounds at least portions of shafts of the interconnect structures and along sides of the microelectronic device. The interconnect structures have first ends thereof protruding above an upper surface of the dielectric layer a distance to increase a warpage limit for a combination of at least the packaged microelectronic device and one other packaged microelectronic device directly coupled to protrusions of the interconnect structures.Type: GrantFiled: November 16, 2016Date of Patent: August 7, 2018Assignee: Invensas CorporationInventors: Ashok S. Prabhu, Rajesh Katkar
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Patent number: 10043772Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip; a second interconnection member disposed on the first interconnection member and the semiconductor chip; and connection terminals disposed on the second interconnection member. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip, and a connection pad and a connection terminal are electrically connected to each other by a pathway passing through the redistribution layer of the first interconnection member.Type: GrantFiled: April 17, 2017Date of Patent: August 7, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Sang Kyu Lee, Jin Gu Kim
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Patent number: 10043753Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The structure includes: a plurality of metal lines formed on an insulator layer; and a dielectric material completely filling a space having a first dimension between metal lines of the plurality of metal lines and providing a uniform airgap with a space having a second dimension between metal lines of the plurality of metal lines. The first dimension is larger than the second dimension.Type: GrantFiled: December 13, 2016Date of Patent: August 7, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Huy Cao, Zhiguo Sun, Joseph F. Shepard, Jr., Moosung M. Chae