Abstract: A method for debouncing an electrical input signal (xin) includes following steps: (1) an input signal (xin) is received and a present value of the input signal (xin) is ascertained; (2) ascertaining whether the present value of the input signal (xin) is above or below at least one predefined limit value (xG); (3) producing a debounce status variable (xE) having a defined initial value; (4) altering the value of the debounce status variable (xE) on the basis of at least whether the value of the input signal (xin) is above or below the at least one limit value (xG), (5) generating an output signal (xout) on the basis of whether the value of the debounce status variable (xE) corresponds to the minimum value (Wmin), to the maximum value (Wmax) or to a value between the minimum value (Wmin) and the maximum value (Wmax).

Abstract: A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.

Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

Abstract: A device includes an epitaxial layer located over a semiconductor substrate, the epitaxial layer and the substrate both having a first conductivity type. A field-effect transistor (FET) includes source and drain regions having an opposite second conductivity type disposed in the epitaxial layer, and a gate structure over the substrate and between the source and drain regions. A diode includes first and second p-type regions and an n-type region all disposed in the epitaxial layer, the n-type region touching the first p-type region. A conductive plug electrically connects the first p-type region to the source region via the substrate.

Abstract: A system may include first and second node, switch, driver, capacitor, and second driver. The first node may be at first voltage. The second node may be at second voltage. The switch may be coupled to the second node and output of the second driver and configured to receive input at third voltage and voltage at fourth voltage and to provide the input to the second node when the fourth voltage is greater than the third voltage. The driver may be coupled to the first and second nodes and configured to receive driver input and to generate intermediate voltage based on the driver input. The capacitor may be coupled to the driver to shift the intermediate voltage. The second driver may be coupled to the second node and the driver and configured to receive second driver input and the shifted intermediate voltage to generate the voltage at the fourth voltage.

Abstract: A locking detecting circuit of a Phase Locked Loop (PLL) circuit includes an output signal counter performing an output signal counting operation of counting an output signal of the PLL circuit during a counting time period, a period determiner performing a period changing operation of decreasing the counting time period until a difference between a current period counting value and a preceding period counting value becomes smaller than a threshold value, and a locking detector detecting a locking of the PLL circuit when the difference between the current period counting value and the preceding period counting value becomes smaller than the threshold value.

Abstract: A clock generator includes an oscillator that generates a clock signal as an output of the clock generator, where the frequency of the clock signal is dependent on a bias current. A feedback circuit receives the clock signal and generates a feedback signal indicative of a frequency of the clock signal. A voltage detector generates a charged voltage using the feedback signal, compares a source voltage with the charged voltage, and generates a detection signal indicative of the comparison between the source voltage and the charged voltage. A control voltage generator generates a control voltage using the detection signal. The bias current is generated by a bias current source using the control voltage.

Abstract: A voltage selection circuit includes a main selection unit, a first re-comparison unit, and a second re-comparison unit. The main selection unit has a first voltage terminal for receiving a first variable voltage, a second voltage terminal for receiving a second variable voltage, and an output terminal for outputting a greater one of the first variable voltage and the second variable voltage as an operation voltage. The first re-comparison unit adjusts the operation voltage according to a greater one of the operation voltage and the first variable voltage, and the second re-comparison unit adjusts the operation voltage according to a greater one of the operation voltage and the second variable voltage.

Abstract: A fractional frequency divider comprises: a fractional frequency divider circuit configured to, by using an integer frequency division signal obtained by dividing an input signal by an integer frequency division ratio, generate a fractional frequency division signal into which the input signal is divided by a fraction frequency division ratio; a latch circuit configured to capture a frequency control signal representing a specified fraction frequency division ratio in synchronization with the fractional frequency division signal; and a control circuit configured to generate an integer control signal for setting an integer frequency division ratio corresponding to a specified fraction frequency division ratio in synchronization with an integer frequency division signal, based on a captured frequency control signal. The fractional frequency divider circuit updates the integer frequency division ratio by referring to the integer control signal in synchronization with the input signal.

Abstract: An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

Abstract: A computer includes a processor and a memory, the memory storing instructions executable by the processor to identify a failure in one of a first, second, or third vehicle power networks and to instruct one of a first display controller connected to the first vehicle power network or a second display controller connected to the second vehicle power network to provide a message to displays respectively connected to the first vehicle power network or the second vehicle power network.

Abstract: A circuit generates a clock signal with a tunable clock period. The circuit comprises capacitors, first tuning circuitry and second tuning circuitry. The first tuning circuitry is configured to adjust the clock period with a first period tuning step based on a first parameter and the second tuning circuit is configured to adjust the clock period with a second period tuning step based on a second parameter. The first period tuning step is different than the second period tuning step.

Abstract: A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

Abstract: The disclosure relates to a communication method and system for converging a 5G communication system for supporting higher data rates beyond a 4G system with an IoT technology. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car or connected car, healthcare, digital education, retail, security and safety-related services.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transmit signals in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.

Abstract: A technique for tuning a ladder-shaped inductor that achieves a finer tuning resolution by severing one or more shorts, skipping the severing of one or more shorts, and severing one or more subsequent shorts within the ladder-shaped inductor. This technique can be applied to a voltage-controlled oscillator using a differential or single-ended ladder-shaped inductor as part of the resonant circuit. Within an oscillator, such a technique provides for a more precise modulation of the effective inductance of the ladder-shaped inductor, which enables an improved tuning resolution of the operating frequency of the oscillator.

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

Abstract: A single-pole double-throw switch. In some embodiments, the switch includes a first switching transistor connected between a common terminal of the single-pole double-throw switch and a first switched terminal of the single-pole double-throw switch, a second switching transistor connected between the common terminal of the single-pole double-throw switch and a second switched terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the first switching transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the second switching transistor.

Abstract: A clock recovery circuit includes a multi-phase sampling circuit, a phase comparison circuit, a recovery clock generation circuit, and a phase shifter. The multi-phase sampling circuit includes edge samplers and data samplers. A data signal is input to each of the edge samplers and each of the data samplers. The phase comparison circuit is disposed at an output side of the multi-phase sampling circuit. The recovery clock generation circuit is configured to output multi-phase clock signals. The phase shifter is disposed between the recovery clock generation circuit and the multi-phase sampling circuit and configured to generate a plurality of clock signals to be supplied to the multi-phase sampling circuit by shifting a phase of a first one of the multi-phase clock signals output from the recovery clock generation circuit by a shift amount different from a shift amount of a second one of the multi-phase clock signals.

Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.