Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode outer-encoded bits to generate an LDPC codeword including LDPC information bits and parity bits; a puncturer configured to puncture some of the parity bits included in the LDPC codeword; and a mapper configured to map the LDPC codeword except the punctured parity bits to symbols for transmission to a receiver, wherein the puncturer calculates a number of parity bits to be punctured among the parity bits included in the LDPC codeword based on a number of the outer-encoded bits, a number of the LDPC information bits, and a minimum number of parity bits to be punctured among the parity bits included in the LDPC codeword.

Abstract: The present disclosure relates to a memory device comprising: an array of memory cells; a plurality of boundary cells able to manage serial and parallel data; mixed pads connected to the memory cells through low speed paths, the mixed pads being configured to be contacted by probes of a testing machine; high speed pads connected to the boundary cells through high speed paths; a three state multiplexer block connected to the memory cells and to the boundary cells and configured to receive thereto at least a first input signal and a second input signal, the three state multiplexer block being also connected to the mixed pads; ESD networks connected to the mixed pads; an enabling circuit connected to one of the mixed pads, configured to receive an external enabling signal and to provide the three state MUX with an internal enabling signal; wherein the enabling circuit comprises: a tester presence detector circuit connected to the mixed pad; and a logical gate having respective input terminals connected to t

Abstract: A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a generation matrix; transforming the generating matrix into a systematic form, wherein the transformed generating matrix is composed of a parity matrix and a check matrix; sorting rows of the parity matrix according to row weights; determining a number of rows in the parity matrix to be truncated; generating a truncated parity matrix by keeping the sorted rows of the P matrix that have weights less than or equal to weights of the truncated rows of the P matrix so as to minimize a number of logic gate operations; and forming an error correction circuit with the number of logic gate operations minimized according to the truncated P matrix to correct the error of the codeword.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: The data collection management device (10) is connected via a network to a plurality of communication devices (20) performing cyclic communication and includes: a network configuration storage (17) to store network configuration information indicating the communication devices participating in the cyclic communication; a data receiving unit (11) to receive communication data multicast from each communication device (20); a received data storage (12) to store the received communication data as collected data; a received data determination unit (13) to determine whether there is missing data in the collected data and identify unreceived communication data, based on information specifying communication cycles included in the collected data, on information specifying sender communication devices included in the collected data, and on network configuration information; and a retransmission requesting unit (15) to transmit a retransmission request of the unreceived communication data to one of the plurality of comm

Abstract: Indexing-based feedback codes and methods of use are disclosed herein. An example method includes determining error correction for a received packet having errors, generating an index of the error correction, the index including error positions for the errors in the received packet, and transmitting the index to a decoder receiver. The receiver using the index to correct the errors in the packet.

Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

Abstract: A method for testing a memory area. The method includes jumping from a destination address to a source address, reading a data word at the source address after jumping to the source address, and examining the data word. The source address was determined based on a static test.

Abstract: A system and method for optimizing seasoning trim values based on form factors in memory sub-system manufacturing. An example method includes selecting a baseline set of trim values based on a set of memory sub-system form factors; generating a first modified set of trim values for seasoning operations by modifying a first trim value of the baseline trim values; causing each memory sub-system of a plurality of memory sub-systems to perform seasoning operations using the first modified set of trim values; responsive to determining that a memory sub-system of the plurality of memory sub-system failed to satisfy a predetermined criterion, determining whether the memory sub-system is extrinsically defective; responsive to determining that the memory sub-system is extrinsically defective, removing the extrinsically defective memory sub-system from the set of memory sub-systems; and generating a second modified set of trim values for seasoning operations.

Abstract: An integrated circuit self-repair method and an integrated circuit thereof are provided. The integrated circuit self-repair method includes: transmitting, by a main register, a predetermined logic state to at least three registers, and setting the at least three registers to the predetermined logic state; outputting, according to the predetermined logic state in the at least three registers, the predetermined logic state to drive a controlled circuit to perform a function; and when a minority of the at least three registers are changed to an opposite logic state due to an emergency occurring at an input power source, outputting the predetermined logic state according to the predetermined logic state of the remaining registers, and transmitting the predetermined logic state back to the register that is in the opposite logic state, to correct the opposite logic state to the predetermined logic state.

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

Abstract: Methods and systems of managing data transfers in a fixture. One system includes fixtures comprising: a communication interface; and a processor configured to optimize download efficiency by: receiving, from a remote device via the communication interface, a file comprising a plurality of data blocks, wherein each of the plurality of data blocks comprise a unique cyclical redundancy check (CRC) value and a payload; determining, for each of the plurality of data blocks, a check value based on a polynomial division of the respective payload; determining an error in at least one of the plurality of data blocks based on a comparison between each of the respective CRC values and the respective check values; and providing, to the remote device via the communication interface, a request for retransmission of each of the at least one of the plurality of data blocks with the determined error.

Abstract: An embedded logic analyzer of an integrated circuit includes a comparison block configured to generate a capture data signal and a plurality of comparison enable signals based on an input data signal from one of function blocks included in the integrated circuit such that the comparison enable signals are activated respectively based on different comparison conditions; an operation block configured to perform a logic operation on the comparison enable signals to generate a data enable signal indicating a data capture timing; and packer circuitry configured to generate a packer data signal including capture data and capture time information based on the capture data signal, the data enable signal and a time information signal.

Abstract: Methods, systems, and devices for testing of multi-level signaling associated with a memory device are described. A tester may be used to test one or more operations of a memory device. The memory device may be configured to communicate data using a modulation scheme that includes three or more symbols. The tester may be configured to communicate data using a modulation scheme that includes three or fewer symbols. Techniques for testing the memory device using such a tester are described.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

Abstract: On-chip spread spectrum characterization including obtaining, from a skitter circuit, skitter data comprising a spread width corresponding to an amplitude of a spread of a spread spectrum clock signal; setting an offset pointer to a center of the spread width corresponding to the amplitude of the spread; retrieving, for each of a number of reference clock cycles, edge data indicating a location, within the spread width, of an edge of the spread spectrum during the reference clock cycle; incrementing, using the edge data, an offset counter for each reference clock cycle during which the edge of the spread spectrum crosses the offset pointer; and calculating a frequency of the spread spectrum using the offset counter and the number of reference clock cycles.

Abstract: An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a current value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.

Abstract: The present disclosure discloses a method and an apparatus for testing an artificial intelligence chip test, a device and a storage medium, and relates to the field of artificial intelligence. The specific implementation solution is: the target artificial intelligence chip has multiple same arithmetic units, the method includes: obtaining scale information of the target artificial intelligence chip; determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information; dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a DFT test on the arithmetic unit arrays, respectively, if it is determined that the test condition of the arithmetic unit array level is satisfied; performing the DFT test on the arithmetic units, respectively, if it is not determined that the test condition of the arithmetic unit array level is not satisfied.

Abstract: Memories, and their operation, might include a plurality of content addressable memory (CAM) cells each for storing a respective data value, a match signal generator configured to generate an indication whether each CAM cell of the plurality of CAM cells indicates a match between its respective data value and a respective received signal value, and a plurality of storage elements each for storing a respective data value, wherein each storage element of the plurality of storage elements corresponds to a respective CAM cell of the plurality of CAM cells in a one-to-one relationship, and wherein each storage element of the plurality of storage elements is responsive to the indication of the match signal generator to generate a data signal indicative of the respective data value of that storage element if a match of their corresponding CAM cells is indicated.

Abstract: An embodiment may involve a network interface module; volatile memory configured to temporarily store data packets received from the network interface module; high-speed non-volatile memory; an interface connecting to low-speed non-volatile memory; a first set of processors configured to perform a first set of operations that involve: (i) reading the data packets from the volatile memory, (ii) arranging the data packets into chunks, each chunk containing a respective plurality of the data packets, and (iii) writing the chunks to the high-speed non-volatile memory; and a second set of processors configured to perform a second set of operations in parallel to the first set of operations, where the second set of operations involve: (i) reading the chunks from the high-speed non-volatile memory, (ii) compressing the chunks, (iii) arranging the chunks into blocks, each block containing a respective plurality of the chunks, and (iv) writing the blocks to the low-speed non-volatile memory.