Abstract: A thermal treatment apparatus 1 includes a reaction tube 2 for containing wafers 10 contaminated with organic substances having a heater 12 capable of heating the reaction tube; a first gas supply pipe 13 for carrying oxygen gas into the reaction tube 2; and a second gas supply pipe 14 for carrying hydrogen gas into the reaction tube 2. Oxygen gas and hydrogen gas are supplied through the first gas supply pipe 13 and the second gas supply pipe 14, respectively, into the reaction tube 2, and the heater 12 heats the reaction tube 2 at a temperature capable of activating oxygen gas and hydrogen gas. A combustion reaction occurs in the reaction tube 2 and thereby the organic substances adhering to the wafers 10 are oxidized, decomposed and removed.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof.

Abstract: Disclosed is a method of forming a capacitor of a semiconductor device which can secure a desired leakage current characteristic while securing a desired charging capacitance. The inventive method of forming a capacitor of a semiconductor device comprises steps of: forming a bottom electrode on a semiconductor substrate with a storage node contact so that the bottom electrode is connected with the storage node contact; plasma-nitrifying the bottom electrode to form a first nitrification film on the surface of the bottom electrode; forming a LaTbO dielectric film on the bottom electrode including the first nitrification film; plasma-nitrifying the LaTbO dielectric film to form a second nitrification film on the surface of the LaTbO dielectric film; and forming a top electrode on the LaTbO dielectric film including the second nitrification film.

Abstract: A process for PECVD of selected material films on a substrate comprising the steps of placing a substrate in a PECVD chamber and maintaining the chamber under vacuum pressure while introducing a precursor gas, a reactant gas, and an ionization enhancer agent into the chamber. A plasma is generated from the gases within the chamber. The energy generating the plasma causes the formation of charged species. The resulting charged species of the ionization enhancer agent assists in the formation of chemically reactive species of at least the precursor.

Abstract: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.

Abstract: Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer (15) of a substantially single-crystal semiconductor (e.g., doped silicon) attached to a support substrate (20) composed of an oxide glass or an oxide glass-ceramic. The oxide glass or oxide glass-ceramic is preferably transparent and preferably has a strain point of less than 1000° C., a resistivity at 250° C. that is less than or equal to 1016 ?-cm, and contains positive ions (e.g., alkali or alkaline-earth ions) which can move within the glass or glass-ceramic in response to an electric field at elevated temperatures (e.g., 300–1000° C.). The bond strength between the semiconductor layer (15) and the support substrate (20) is preferably at least 8 joules/meter2. The semiconductor layer (15) can include a hybrid region (16) in which the semiconductor material has reacted with oxygen ions originating from the glass or glass-ceramic.

Abstract: A method of plasma doping in which dilution of B2H6 is maximized for enhanced safety and stable plasma generation and sustention can be carried out without lowering of doping efficiency and in which the amount of dopant injected can be easily controlled. In particular, a method of plasma doping characterized in that B2H6 gas is used as a material containing doping impurity while He is used as a substance of high dissociation energy and that the concentration of B2H6 in mixed gas is less than 0.05%.

Abstract: The present invention provides system and apparatus for use in processing wafers. The new system and apparatus allows for the production of thinner wafers that at same time remain strong. As a result, the wafers produced by the present process are less susceptible to breaking. The unique system also offers an improved structure for handling thinned wafers and reduces the number of processing steps. This results in improved yields and improved process efficiency.

Abstract: To provide a method of forming a wiring for the purpose of providing a semiconductor device, which is superior in reliability and cost performance. Further, to provide methods of manufacturing a semiconductor device and a display device by using the method of forming the wiring according to the present invention. According to the present invention, when a wiring material and the like is directly patterned on a substrate mainly having an insulating surface by droplet discharging method, a wiring is formed at a position including at least an opening in contact with an underlying portion on an insulating film provided with the opening by dropping a liquid droplet containing a conductive composition by droplet discharging method. By heating the substrate with the wiring formed thereon, a surface of the wiring on the opening and a surface of the wiring other than the wiring on the opening are approximately leveled, and the opening is filled.

Abstract: A method of producing an insulator thin film, for forming a thin film on a substrate by use of the atomic layer deposition process, includes a first step of forming a silicon atomic layer on the substrate and forming an oxygen atomic layer on the silicon atomic layer, and a second step of forming a metal atomic layer on the substrate and forming an oxygen atomic layer on the metal atomic layer, wherein the concentration of the metal atoms in the insulator thin film is controlled by controlling the number of times the first step and the second step are carried out.

Abstract: In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range.

Abstract: A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.

Abstract: A method for producing a field effect transistor having source/drain electrodes of metal single-layer film firmly adhering to the gate insulating film is provided. The method includes forming a gate electrode on a support, forming a gate insulating film on the support and the gate electrode, performing treatment with a silane coupling agent on the surface of the gate insulating film, forming source/drain electrodes of metal single-layer film on the gate insulating film which has been treated with a silane coupling agent, and forming a channel-forming region of semiconductor layer on the gate insulating film held between the source/drain electrodes.

Abstract: A method of fabricating a semiconductor-on-insulator structure from a pair of semiconductor wafers, includes forming an oxide layer on at least a first surface of a first one of the wafers and performing a bonding enhancement implantation step by ion implantation of a first species in the first surface of at least either of the pair of wafers. The method further includes performing a cleavage ion implantation step on one of the pair of wafers by ion implanting a second species to define a cleavage plane across a diameter of the wafer at the predetermined depth below the top surface of the one wafer. The wafers are then bonded together by placing the first surfaces of the pair of wafers onto one another so as to form an semiconductor-on-insulator structure.

Abstract: A system and method for hydrogen (H) exfoliation are provided for attaching silicon-on-insulator (SOI) fabricated circuits to carrier substrates. The method comprises: providing a SOI substrate, including a silicon (Si) active layer and buried oxide (BOX) layer overlying a Si substrate; forming a circuit in the Si active layer; forming a blocking mask over selected circuit areas; implanting H in the Si substrate; annealing; removing the blocking mask; in response to the H implanting, forming a cleaving plane in the Si substrate; bonding the circuit the top oxide layer to the carrier substrate; and, cleaving the Si substrate. More specifically, the cleaving plane is formed along a horizontal peak concentration (Rp) H layer in the Si substrate and along the buried oxide layer interface.

Abstract: Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer (15) of a substantially single-crystal semiconductor (e.g., doped silicon) attached to a support substrate (20) composed of an oxide glass or an oxide glass-ceramic. The oxide glass or oxide glass-ceramic is preferably transparent and preferably has a strain point of less than 1000° C., a resistivity at 250° C. that is less than or equal to 1016 ?-cm, and contains positive ions (e.g., alkali or alkaline-earth ions) which can move within the glass or glass-ceramic in response to an electric field at elevated temperatures (e.g., 300–1000° C.). The bond strength between the semiconductor layer (15) and the support substrate (20) is preferably at least 8 joules/meter2. The semiconductor layer (15) can include a hybrid region (16) in which the semiconductor material has reacted with oxygen ions originating from the glass or glass-ceramic.

Abstract: A method of producing a calibration wafer having at least a predetermined emissivity, including providing a wafer of semiconductor material; subjecting the bulk material of the wafer to doping with foreign atoms and/or generating lattice defects to obtain the predetermined emissivity; and coating the wafer to obtain a further optical characteristic.

Abstract: A metal filled damascene structure with improved electromigration resistance and method for forming the same, the method including providing a semiconductor process wafer comprising damascene openings; and, depositing metal and at least one metal dopant according to an ECD process to from a metal filled damascene comprising a doped metal alloy portion.

Abstract: A method for forming a standoff structure for packaging devices, e.g., optical devices, integrated circuit devices. The method includes providing a substrate, e.g., silicon wafer. The substrate includes a first surface region, a second surface region, and a thickness defined between the first surface region and the second surface region. The method includes protecting selected portions of the first surface region using a masking layer while leaving a plurality of unprotected regions. Preferably, each of the unprotected regions is to be associated with an opening through the thickness of the substrate. The method causes removal of the plurality of unprotected regions to form a plurality of openings through the thickness of the substrate to provide a resulting patterned substrate. Each of the openings is bordered by a portion of the selected portions of the first surface region. Preferably, etching techniques, such as wet etch or dry etching, can be used, depending upon the embodiment.