Abstract: A micro-electro-mechanical (MEM) device and an electronic device are fabricated on a common substrate by fabricating the electronic device comprising a plurality of electronic components on the common substrate, depositing a thermally stable interconnect layer on the electronic device, encapsulating the interconnected electronic device with a protective layer, forming a sacrificial layer over the protective layer, opening holes in the sacrificial layer and the protective layer to allow the connection of the MEM device to the electronic device, fabricating the MEM device by depositing and patterning at least one layer of amorphous silicon, and removing at least a portion of the sacrificial layer. In this way, the MEM device can be fabricated after the electronic device on the same substrate.

Abstract: A method of producing a ferroelectric capacitor includes the steps of: preparing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; laminating sequentially a metal layer, a first conductive layer, a ferroelectric layer, and a second conductive layer on the first insulating layer to form a capacitor forming laminated layer; forming an etching mask forming layer with strontium tantalate or strontium niobate; forming a silicon oxide layer on the etching mask forming layer for covering a ferroelectric capacitor forming area; forming an etching mask through wet etching of the etching mask forming layer with the silicon oxide layer; and forming a lamination formed of a barrier metal, a lower electrode, a ferroelectric layer, and an upper electrode through dry etching of the capacitor forming laminated layer with the etching mask.

Abstract: A method of fabricating a pixel cell having a shutter gate structure. First and second charge barriers are respectively created between a photodiode and a first charge storage region and between the first storage region and a floating diffusion region. A global shutter gate is formed to control the charge barrier and transfer charges from the photodiode to the first charge storage region by effectively lowering the first charge barrier. A transfer transistor acts to transfer charges from the first storage region to the floating diffusion region by reducing the second charge barrier.

Abstract: It is a general object of the present invention to provide an improved method of fabrication in the formation of an improved copper metal diffusion barrier layer having the structure, W/WSiN/WN, in single and dual damascene interconnect trench/contact via processing with 0.10 micron nodes for MOSFET and CMOS applications. The diffusion barrier is formed by depositing a tungsten nitride bottom layer, followed by an in situ SiH4/NH3 or SiH4/H2 soak forming a WSiN layer, and depositing a final top layer of tungsten. This invention is used to manufacture reliable metal interconnects and contact vias in the fabrication of MOSFET and CMOS devices for both logic and memory applications and the copper diffusion barrier formed, W/WSiN/WN, passes a stringent barrier thermal reliability test at 400° C. Pure single barrier layers, i.e., single layer WN, exhibit copper punch through or copper spiking during the stringent barrier thermal reliability test at 400° C.

Abstract: A resistance element of a semiconductor device includes a first resistance pattern and a second resistance pattern formed adjacent to the first resistance pattern at a lower level, wherein the second resistance pattern is defined by the first resistance pattern in a self-aligned relationship and connected to the first resistance pattern in series.

Abstract: We describe a system of electronically active inks which may include electronically addressable contrast media, conductors, insulators, resistors, semiconductive materials, magnetic materials, spin materials, piezoelectric materials, optoelectronic, thermoelectric or radio frequency materials. We further describe a printing system capable of laying down said materials in a definite pattern. Such a system may be used for instance to: print a flat panel display complete with onboard drive logic; print a working logic circuit onto any of a large class of substrates; print an electrostatic or piezoelectric motor with onboard logic and feedback or print a working radio transmitter or receiver.

Abstract: Process for forming a fragile layer inside of a single crystalline substrate near one of the substrate surfaces. The fragile layer is created by collecting hydrogen in high concentration at a desired depth. The hydrogen layer is collected on a seed layer. The seed layer is formed by ion implantation of non-doping species and annealing. The implantation introduces defects that are capable to trap hydrogen, and annealing confines the seed layer making it flat and thin. Then protium hydrogen ions are implanted at elevated temperature. The protium implantation depth is bigger than the depth of the seed layer. The implanted protium moves to the seed layer and trap there. The process is useful for making silicon-on-insulator (SOI) wafers. SOI with an ultrathin superficial silicon layer of high quality can be obtained. Hydrogen can be implanted at high dose rate, and thus the SOI wafers can be manufactured with high throughput and low cost.

Abstract: The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions being nearer the dielectric material than the other. The portion of the metal nitride nearest the dielectric material is formed from a non-halogenated metal-containing precursor, and the portion of the metal nitride further from the dielectric material is formed from a halogenated metal-containing precursor. The methodology of the present invention can be utilized for forming capacitor constructions, with the portion of the metal nitride formed from the halogenated metal-containing precursor being incorporated into a capacitor electrode.

Abstract: A group-III nitride semiconductor stack comprises a single-crystal substrate, a first group-III nitride layer formed on a principal surface of the single-crystal substrate, a graded low-temperature deposited layer formed on the group-III nitride layer and made of nitride in which group-III element composition is continuously changed, and a second group-III nitride layer formed on the graded low-temperature deposited layer.

Abstract: The invention is directed to a vertically emitting laser and a method of manufacturing such a laser having a current aperture and a semiconductor relief. The semiconductor relief and the current aperture are defined in the same processing operation, thereby causing the semiconductor relief and the current aperture to be substantially self-aligned with respect to one another. In addition, such processing results in an area ratio of the semiconductor relief and the current aperture to be substantially self-scaling with respect to processing variations.

Abstract: After ion implantation, thermal ashing is performed using ozone at a pressure of between about 0.01 to about 1000 Torr at below 1000° C. to remove the resist. Since the process includes a substantial amount of ozone, the resist can be completely oxidized, thus leaving no residue or other contaminates to remain on the substrate. Using ozone allows fast resist removal with minimal residue at low temperatures.

Abstract: Concentration of metal element which promotes crystallization of silicon and which exists within a crystalline silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is performed after introducing nickel to an amorphous silicon film 103. Then, laser light is irradiated to diffuse nickel element which is concentrated locally. After that, another heat treatment is performed within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. At this time, HCl or the like is added to the atmosphere. A thermal oxide film 106 is formed in this step. At this time, gettering of the nickel element into the thermal oxide film 106 takes place. Then, the thermal oxide film 106 is removed. Thereby, a crystalline silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.

Abstract: A method of performing quantum well intermixing in a semiconductor device structure uses a sacrificial part of a cap layer, that is removed after QWI processing, to restore the cap surface to a condition in which high performance contacts are still possible.

Abstract: A semiconductor device including: a semiconductor substrate having an integrated circuit and a penetrating hole; an insulating layer formed on an inner surface of the penetrating hole; and a conductive section formed on the insulating layer to penetrate the semiconductor substrate and having a recess on an end surface.

Abstract: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.

Abstract: Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more semiconductor dice having very fine pitch electrical I/O (input/output) elements. The semiconductor dice are temporarily attached to the die carrier in singulated form to enable testing the dice with conventional contact technology. The die carrier may include a flex circuit base substrate and a rigid support frame. Further embodiments comprise materials and methods for attaching the semiconductor dice to the die carrier and for providing a temporary electrical connection with the semiconductor dice during testing. Exemplary materials for providing the temporary electrical connection may comprise a conductive film or tape, a conductive or conductor-filled epoxy, resin or RTV adhesive-based materials, a water-soluble material impregnated with a conductive filler or non-reflowed solder paste.

Abstract: A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer. The first mask layer and second mask layer are etchable by the same etching process. The first and second mask layer are etched. Etch residue is removed from the first and second mask layers. The first mask layer is then selectively removed and the second mask layer remains.

Abstract: A method of fabricating a compound semiconductor layer has steps of forming a first layer made of an oxidizable material on a substrate, forming a second layer made of a compound semiconductor on the first layer, oxidizing the first layer made of the oxidizable material to an oxide layer and forming a third layer made of compound semiconductor that constitutes a semiconductor element on the second layer.

Abstract: This invention relates to a method of depositing a tantalum film in which ?-Ta dominates and to methods of electroplating copper using such films. The films have a thickness of less than 300 nm and are formed by depositing a seed layer of an organic containing low dielectric constant insulating layer and sputtering tantalum onto the seed layer at a temperature below 250° C.

Abstract: A method of manufacturing an element having a microstructure of an excellent grating groove pattern or the like is obtained. This method of manufacturing an element having a microstructure comprises steps of forming a metal layer on a substrate, forming a dot column of concave portions on the surface of the metal layer and anodically oxidizing the surface of the metal layer formed with the dot column of concave portions while opposing this surface to a cathode surface thereby forming a metal oxide film having a grating groove pattern. When the interval between the concave portions of the dot column is reduced, therefore, a linear grating groove pattern having a large depth with a uniform groove width along the depth direction is easily formed in a self-organized manner.