Abstract: A memory card having a memory bus controller is provided which card has a signal processing element preferably a digital signal processor (DSP) thereon, which card is used in a computer system as add-on memory. Also, a method of using such a card in a computer system is provided. The memory bus controller and the signal processing element are programmed to pass all the addresses in the memory on the card and the associated data received from the CPU to the signal processing element where they are stored in memory. The signal processing element is programmed to perform selected operations on the addresses and/data irrespective of whether the signal processing element has control of the system bus. These operations can include keeping track of read/write operations and the locations of these operations. This information can be easily accessed by the computer system and used for memory optimization. The DSP can also “snoop” the memory bus when it is unavailable to the control of the DSP, i.e.

Abstract: A micro processor board of the bus control system comprises an internal bus which address lines, data lines, and control signal lines. The micro processor board also includes a memory connected via the internal bus with the micro processor, registers such as a system control register, and a bus interface circuit. Access to the main memory, the register, or the bus interface which is executed by the micro processor is outputted from an external bus via the bus interface circuit. Thus, the operational status of the micro processor or the internal bus can be traced by tracing the external bus.

Abstract: In an aspect, the invention features a method of storing data in a digital data storage system that includes a plurality of disk drives. The method involves receiving data at the data storage system; compressing the received data to generate a compressed version of the data; storing the received data on a first set of disk drives among the plurality of disk drives; and storing the compressed version of the received data on a parity disk drive so that the parity drive stores data that is redundant of data that is stored on the first set of drives.

Abstract: A disk conforms to a fixed length format and a storage subsystem shapes a CKD format record from a host computer in a fixed length unit to store shaped data therein. A format conversion program reads a fixed length block from the disk and extracts the shaped CKD format data to obtain such information to access a file system as file management information to thereby access the file system. Moreover, in an operation to write data on the disk, the data which the storage subsystem has received from the host computer is shaped in the conversion program into a sequence of data in a format to be written on the disk and then the sequence of data is written in a fixed length format thereon. Resultantly, data can be shared between systems using mutually different data formats to store data in storages.

Abstract: A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The cache design allows two cache requests to be processed simultaneously (dual-ported) and concurrent cache requests to be in-flight (pipelined). The design of the cache allocates a first clock cycle to cache tag and data access and a second cycle is allocated to data manipulation. The memory array circuit design is simplified because the circuits are synchronized to the main processor clock and do not need to use self-timed circuits. The overall logic control scheme is simplified because distinct cycles are allocated to the cache functions.

Abstract: The present invention provides a method and system for reporting disk utilization in a computer system. The method includes collecting at least one parameter pertaining to a disk array in a disk subsystem by a processor in the disk subsystem; transferring the at least one parameter from the processor to an open system host; and calculating disk utilization based upon the at least one parameter. The method and system is able to provide disk utilization which is understandable to the open system host. In a preferred embodiment, the disk utilization is provided by collecting the relevant parameters from the microcode in the processor of the disk subsystem, and then calculating the average disk utilization per disk based upon the parameters. Thus, an open system host is able to obtain a useful characteristic for determining the performance of the disk subsystem.

Abstract: A method and an apparatus for reconfiguring a storage subsystem by performing an ordered sequence of reconfigurations of physical storage volumes of the storage subsystem. The method and apparatus perform a portion of the sequence of reconfigurations, in response to receiving a rollback request, in an order that is reversed with respect to the order of the sequence.

Abstract: Load balancing of activities on physical disk storage devices is accomplished by monitoring reading and writing operations to blocks of contiguous storage locations on the physical disk storage devices. Statistics accumulated over an interval are then used to obtain access activity values for each block and each physical disk drive. A method is disclosed for efficiently generating disk access time based upon these statistics.

Abstract: A data processing system is provided with a flash memory including a plurality of blocks and capable of erasing stored data collectively in units of block and a memory control unit for accessing the flash memory, the memory control unit having a control circuit for formatting the flash memory according to a format information for substantially coinciding each cluster serving as a logical unit of memory region of the flash memory with integer ones of the blocks and a control circuit for determining a size and position of each cluster and carrying out access control for erasing, write-in and reading of data of the flash memory according to the size and position of the determined cluster.

Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.

Abstract: A data processor comprising an adder for adding an address signal and an address conversion data set up by a central processing unit, to decide a converted address signal corresponding to the address signal, and a selector for selecting either of the converted address signal decided by the adder or the address signal, based on the detection signal output from an agreement detection circuit which judges whether the address signal agrees with the original ROM address or not, wherein the processings in the adder and the agreement detection circuit are performed in parallel.

Abstract: A prefetch buffer architecture includes a prefetch buffer connected to a memory unit via a global bus. A continue detect unit is also connected to the global bus via a global bus interface. The continue detect unit examines prefetched data words for a predetermined bit pattern indicating the possible presence of a “continue” command. The continue detect unit may use one or more comparator circuits to compare each prefetched data word with the predetermined bit pattern. Multiple comparator circuits can be used in parallel to simultaneously examine multiple data words. When the continue detect unit determines that a data word contains the predetermined bit pattern, indicating the likely presence of a “continue” command, the prefetch operation is suspended. The data word likely to contain the “continue” command is stored in the prefetch buffer until it is called by a decode unit, which decodes the continue command.

Abstract: A method of recording data, including audio data and control data, to a SCSI drive having both a write mode and a write-verify mode, comprises the steps of initializing the drive to a write mode, receiving recording data and organizing the recording data into SCSI request blocks (SRBs), and checking each SRB to see if it contains a write block. If the SRB includes either no write block or is audio data, then the SRB is recorded by the drive. However, if the SRB includes a write block and no audio data, then the SRB is converted from a write block to a write-verify block and recorded by the drive.

Abstract: Disclosed is a system for caching data. After determining a sequential access of a first memory area, such as a direct access storage device (DASD), a processing unit stages a group of data sets from the first memory area to a second memory, such as cache. The processing unit processes a data access request (DAR) for data sets in the first memory area that are included in the sequential access and reads the requested data sets from the second memory area. The processing unit determines trigger data set from a plurality of trigger data sets based on a trigger data set criteria. The processing unit then stages a next group of data sets from the first memory area to the second memory area in response to reading the determined trigger data set.

Abstract: A method and apparatus which provides a cache management policy for use with a cache memory for a multi-threaded processor. The cache memory is partitioned among a set of threads of the multi-threaded processor. When a cache miss occurs, a replacement line is selected in a partition of the cache memory which is allocated to the particular thread from which the access causing the cache miss originated, thereby preventing pollution to partitions belonging to other threads.

Abstract: A method and apparatus for buffering is provided. A set of buffers is maintained in an ordered list based on a profit value generated for each buffer. The profit value for a buffer reflects multiple access characteristics of the buffer. The list of buffers is partitioned into divisions referred to as buckets. Each bucket contains a set of buffers and is associated with a subrange of the fall range of profit values that may be generated. The bucket that covers the very top of the list is associated with highest profit value subrange, the bucket that covers the bottom of the list is associated with the lowest profit value subrange. When data is first placed in a buffer, the buffer's position within the buffer list is not immediately based on its profit value. Instead, an access history is first accumulated for the buffer and, once accumulated, the buffer's profit value earns the buffer's place in the list.

Abstract: A system and method for operating an associative memory cache device in a computer system. The system comprises a search client configured to search for data in a caching associative memory such as a content addressable memory (CAM); a caching associative memory element coupled to the search client for generating a matching signal; and a associative memory element coupled to the caching associative element configured to search for data not stored in the caching associative memory element. The search client issues a search request for data to associative cache element. If the matching data is found there, then such matching data is returned to the search client. Alternatively, if the data is not found, then the search request is issued to the main associative memory. The least frequently used data or the least recently used data in the associative memory cache are replaced with the matching data and the higher priority data.

Abstract: An apparatus and method for allocating a memory in a cache aware manner are provided. An operating system can be configured to partition a system memory into regions. The operating system can then allocate corresponding portions within each region to various programs that include the operating system and applications. The portions within each region of the system memory can map into designated portions of a cache. The size of a portion of memory allocated for a program can be determined according to the needs of the program.

Abstract: Systems and methods consistent with the present invention allocate memory of a memory array by partitioning the memory array into subheaps dedicated to frequently used memory blocks. To this end, the system collects memory statistics on memory usage patterns to determine memory block sizes most often used in the memory array. The system uses these statistics to partition the memory array into a main heap and at least one memory subheap. The system then allocates or deallocate memory of the memory array using the memory subheap. Furthermore, the system allocates memory of the memory subheap only for memory blocks having one of the memory block sizes most often used in the memory array.

Abstract: A device controller for interfacing a host computer with an external storage device has an autohost controller. The device controller, at the end of a read operation, fills a memory buffer with data blocks contiguous with the read operation. On a subsequent read operation, the autohost controller checks the subsequent read operation and, if the requested data is within the memory buffer, directs the device controller to transfer the data from the memory buffer without intervention from an external microprocessor. If the autohost controller does not intervene, the device controller operates under the control of the microprocessor, as normal.