Abstract: Method and structure for enhancing channel performance in a vertical gate all-around device, which provides a device comprising: a source region; a drain region aligned substantially vertically to the source region; a channel structure bridging between the source region and the drain region and defining a substantially vertical channel direction; and a gate structure arranged vertically between the source region and the drain region and surrounding the channel structure. The channel structure comprises a plurality of channels extending substantially vertically abreast each other, each bridging the source region and the drain region, and at least one stressor interposed between each pair of adjacent channels and extending substantially along the vertical channel direction; the stressor affects lateral strain on the adjacent channels, thereby straining the channels in the vertical channel direction.

Abstract: A semiconductor device includes a first fin structure extending from a semiconductor substrate. A second fin structure is disposed over the first fin structure. The second fin structure includes a first layer including a first semiconductor material. The second fin structure further includes a second layer including a second semiconductor material disposed over the first layer. The second layer has a vertical sidewall. The second semiconductor material is different from the first semiconductor material. A gate structure is disposed over the semiconductor substrate and wraps around the first and second layers of the second fin structure.

Abstract: A method for fabricating silicon-on-insulator (SOI) semiconductor devices, wherein the piezoresistive pattern is defined within a blanket doped layer after fusion bonding. This new method of fabricating SOI semiconductor devices is more suitable for simpler large scale fabrication as it provides the flexibility to select the device pattern/type at the latest stages of fabrication.

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.

Abstract: A method for preparing a perovskite solar cell by a non-deposition method is provided. Particularly, the method includes preparing a first substrate by forming a hole transport layer on a light absorbing layer in a semi-dried state and pressurizing and drying a second substrate including an opposing electrode to the first substrate.

Abstract: Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction.

Abstract: A method of manufacturing an organic light-emitting display device includes: preparing a substrate including pixel electrodes; forming a pixel defining layer on the substrate, the pixel defining layer exposing a central portion of each of the pixel electrodes and covering an edge portion of each of the pixel electrodes; forming partitioning walls in correspondence with at least a portion of an upper surface of the pixel defining layer, the partitioning walls including a first resin; removing a solvent in the partitioning walls by baking the partitioning walls; forming a first mask layer filling a space between the partitioning walls and exposing a first pixel electrode among the pixel electrodes, the first mask layer including a second resin; and forming a first intermediate layer on the first pixel electrode.

Abstract: In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions. A second portion of the empty region is filled with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width and comprises a second plurality of partitions.

Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, the tunnel barrier layer is expressed by a composition formula of AB2Ox (0<x?4), and has a spinel structure in which cations are arranged in a disordered manner, the tunnel barrier layer has a lattice-matched portion and a lattice-mismatched portion, A is a divalent cation of plural non-magnetic elements, B is an aluminum ion, and in the composition formula, the number of the divalent cation is smaller than half the number of the aluminum ion.

Abstract: A substrate and a manufacturing method thereof, and a display device are provided. The substrate comprises a base substrate (101), a metal black matrix (111) and an anti-reflection pattern (112A, 112B) for reducing optical reflectivity of the metal black matrix (111), which are arranged on the base substrate (101), and the anti-reflection pattern (112A, 112B) is arranged on a side of the metal black matrix (111) close to a light emission side of the substrate. The anti-reflection pattern (112A, 112B) reduces reflectivity of the metal black matrix (111) on outside ambient light, increases a display contrast of a display device that includes the substrate, and thus improves display quality of the pictures.

Abstract: A light-emitting device is provided. The light-emitting device comprises The light-emitting device comprises a light-emitting stack comprising a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; and a third semiconductor layer on the light-emitting stack and comprising a first sub-layer, a second sub-layer and a roughened surface, wherein the first sub-layer has the same composition as that of the second sub-layer, and the second sub-layer is farther from the light-emitting stack than the first sub-layer; wherein the first sub-layer and the second sub-layer each comprises a Group III element and a Group V element, and an atomic ratio of the Group III element to the Group V element of the first sub-layer is less than an atomic ratio of the Group III element to the Group V element of the second sub-layer.

Abstract: A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.

Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.

Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.

Abstract: A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.

Abstract: A method includes forming a first isolation region in a substrate, wherein a top surface of the first isolation region is level with a top surface of the substrate, removing an upper portion of the first isolation region to form a recess, depositing a gate dielectric layer over the first isolation region, forming a gate electrode layer over the gate dielectric layer and patterning the gate electrode layer to form a gate electrode region, wherein a first portion of the gate electrode region is vertically aligned with the first isolation region and a second portion of the gate electrode region is formed over the substrate, and where a top surface of the first portion is lower than a top surface of the second portion.

Abstract: A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.

Abstract: A method and apparatus for dry etching pure Cu and Cu-containing layers for manufacturing integrated circuits. The invention uses a directional beam of O-atoms with high kinetic energy to oxidize the Cu and Cu-containing layers, and organic compound etching reagents that react with the oxidized Cu to form volatile Cu-containing etch products. The invention allows for low-temperature, anisotropic etching of pure Cu and Cu-containing layers in accordance with a patterned hard mask or photoresist.