Abstract: In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions. A second portion of the empty region is filled with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width and comprises a second plurality of partitions.

Abstract: A method of improving micro-loading effect when recess etching a tungsten layer. A substrate having trenches thereon is provided. A tungsten layer is deposited on the substrate and in the trenches. A planarization process is performed to form a planarization layer on the tungsten layer. A first etching process is performed to etch the planarization layer and the tungsten layer with an etch selectivity of planarization layer:tungsten layer=1:1 until the planarization layer is completely removed. A second etching process is performed to etch the remainder of the tungsten layer to recess the tungsten layer within the trenches.

Abstract: A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.

Abstract: A ?LED including an epitaxial stacked layer, a first electrode and a second electrode is provided. The epitaxial stacked layer includes a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor layer. The epitaxial stacked layer has a first mesa portion and a second mesa portion to form a first type conductive region and a second type conductive region respectively. The first electrode is disposed on the first mesa portion. The second electrode is disposed on the second mesa portion. The second electrode contacts the first type doped semiconductor layer, the light emitting layer and the second type doped semiconductor layer located at the second mesa portion. Moreover, a manufacturing method of the ?LED is also provided.

Abstract: A method of making a circuit device includes forming core circuitry. The core circuitry includes a doped region in the core circuit. The method further includes implanting a first set of guard rings around a periphery of the core circuitry. The first set of guard rings has a first dopant type. Implanting the first set of guard rings includes implanting the first set of guard rings spaced from the doped region. The method further includes implanting a second set of guard rings having a second dopant type, wherein the second dopant type being opposite to the first dopant type. At least one guard ring of the second set of guard rings is around a periphery of at least one guard ring of the first set of guard rings.

Abstract: The number of masks and photolithography processes used in a manufacturing process of a semiconductor device are reduced. A first conductive film is formed over a substrate; a first insulating film is formed over the first conductive film; a semiconductor film is formed over the first insulating film; a semiconductor film including a channel region is formed by etching part of the semiconductor film; a second insulating film is formed over the semiconductor film; a mask is formed over the second insulating film; a first portion of the second insulating film that overlaps the semiconductor film and second portions of the first insulating film and the second insulating film that do not overlap the semiconductor film are removed with the use of the mask; the mask is removed; and a second conductive film electrically connected to the semiconductor film is formed over at least part of the second insulating film.

Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A conductive feature over a substrate is provided. A first dielectric layer is deposited over the conductive feature and the substrate. A via-forming-trench (VFT) is formed in the first dielectric layer to expose the conductive feature and the substrate around the conductive feature. The VFT is filled in by a sacrificial layer. A via-opening is formed in the sacrificial layer to expose the conductive feature. A metal plug is formed in the via-opening to connect to the conductive feature. The sacrificial layer is removed to form a surrounding-vacancy around metal plug and the conductive feature. A second dielectric layer is deposited over the substrate to seal a portion of the surrounding-vacancy to form an enclosure-air-gap all around the metal plug and the conductive feature.

Abstract: The disclosure is directed to an integrated circuit structure for joining wafers and methods of forming same. The IC structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. The sidewall of the metallic pillar may be free of the solder material. The method may include: forming a metallic pillar over a substrate, the metallic pillar having an upper surface; forming a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and forming a solder material over the upper surface of the metallic pillar within and constrained by the wetting inhibitor layer.

Abstract: In some embodiments, the present disclosure relates to a vertical transistor device, and an associated method of formation. The transistor device has a source region over a substrate and a vertical channel bar over the source region. The vertical channel bar has a bottom surface with an elongated shape. A conductive gate region is separated from sidewalls of the vertical channel bar by a gate dielectric layer. The conductive gate region has a vertical leg and a horizontal leg protruding outward from a sidewall of the vertical leg. A dielectric layer vertically extends from a plane extending along an uppermost surface of the conductive gate region to a position surrounded by the conductive gate region. A drain contact is over the vertical channel bar.

Abstract: According to an embodiment of the present disclosure, a chip package including at least one chip, a first encapsulation layer, a redistribution layer, and a second encapsulation layer is provided. The at least one chip has an active surface, a back surface opposite to the active surface, and sidewall surfaces connecting the active surface and the back surface. The first encapsulation layer covers the sidewall surfaces. The first encapsulation layer has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the active surface and the first surface, and electrically connected to the at least one chip. The second encapsulation layer is disposed on the back surface and the second surface. A thermal expansion coefficient of the second encapsulation layer is less than a thermal expansion coefficient of the first encapsulation layer. Chip packaging methods are also provided.

Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate; patterning a first active region, a second active region and an isolation between the first active region and the second active region over the substrate; disposing an inter-level dielectric (ILD) over the substrate; forming a first gate extended over the first active region, the isolation and the second active region; and forming a second gate over the first active region and the second active region, wherein the second gate includes a first section disposed over the first active region and a second section disposed over the second active region, a portion of the ILD is disposed between the first section and the second section.

Abstract: A stacked semiconductor device is formed by implanting ions through dielectric and conductive structures of a first substrate to define a cleave plane in the first substrate, cleaving the first substrate at the cleave plane to obtain a cleaved layer including the dielectric and conductive structures, bonding at least one die to the first substrate, the at least one die having a smaller width than a width of the first substrate, depositing a planarization material over the at least one die, planarizing the planarization material to form a planarized upper surface over the at least one die, and stacking a third substrate on the planarized upper surface.

Abstract: A method of manufacturing a solar cell can include forming a silicon oxide film on a semiconductor substrate and successively exposing the silicon oxide film to a temperature in a range of 570° C. to 700° C. to anneal the silicon oxide film.

Abstract: Implementations disclosed herein relate to methods for controlling substrate outgassing. In one implementation, the method includes removing oxides from an exposed surface of a substrate in an inductively coupled plasma chamber, forming an epitaxial layer on the exposed surface of the substrate in an epitaxial deposition chamber, and performing an outgassing control of the substrate by subjecting the substrate to a first plasma formed from a first etch precursor in the inductively coupled plasma chamber at a first chamber pressure, wherein the first etch precursor comprises a hydrogen-containing precursor, a chlorine-containing precursor, and an inert gas, and subjecting the substrate to a second plasma formed from a second etch precursor in the inductively coupled plasma chamber at a second chamber pressure that is higher than the first chamber pressure, wherein the second etch precursor comprises a hydrogen-containing precursor and an inert gas.

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

Abstract: Sensor packages and manners of formation are described. In an embodiment, a sensor package includes a supporting die characterized by a recess area and a support anchor protruding above the recess area. A sensor die is bonded to the support anchor such that an air gap exists between the sensor die and the recess area. The sensor die includes a sensor positioned directly above the air gap.

Abstract: A method for fabricating a light emitting device, comprising: forming a plurality of light emitting stacked layers above a substrate; forming and patterning a current blocking (CB) layer on the light emitting stacked layers; forming a transparent conductive layer covering the light emitting stacked layers and the current blocking layer; etching the transparent conductive layer and exposing a reserved region for a first pad electrode and a mesa structure, respectively; and etching an exposed portion of the light emitting stacked layers and a portion of the current blocking layer to form a remaining current blocking layer, the mesa structure and a first opening.

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.

Abstract: The invention relates to the field of laser annealing, and discloses a laser annealing device, a production process of a polycrystalline silicon thin film, and a polycrystalline silicon thin film produced by the same. The laser annealing device comprises an annealing chamber, in which a laser generator is provided, wherein an annealing window, through which the laser passes, and two light-cutting plates oppositely provided above the annealing window are also provided in the annealing chamber, wherein the light-cutting end face of each of the light-cutting plates is a wedge-shaped end face. In technical solutions of the invention, since the light-cutting end face is a wedge-shaped end face, the included angle formed by the reflected beam, which is formed by the reflection of the incident beam arriving at the light-cutting end face, and the ingoing beam, which passes through the annealing window, is relatively large, and the vibrating directions of them differ relatively greatly.