Patents Examined by Bac Au
  • Patent number: 9660098
    Abstract: Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer. In the semiconductor device, the defect density in the oxide semiconductor layer is reduced.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: May 23, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Sachiaki Tezuka, Tetsuhiro Tanaka, Toshihiko Takeuchi, Hideomi Suzawa, Suguru Hondo
  • Patent number: 9660209
    Abstract: The present invention provides a method for manufacturing an OLED device and an OLED device manufactured therewith. The method for manufacturing an OLED device includes: (1) providing a substrate and forming, in sequence, an anode and a hole transporting layer on the substrate; (2) forming an emissive layer on the hole transporting layer through a solution film casting process, wherein the emissive layer comprises a red sub-pixel, a green sub-pixel, and a blue sub-pixel, of which at least one sub-pixel is formed of a quantum dot and at least one sub-pixel is formed of an organic light-emitting material; (3) forming, in sequence, an electron transporting layer and a cathode on the emissive layer; and (4) providing a package cover plate, which is set above the cathode, wherein the substrate and the package cover plate are bonded together by sealing enclosing resin to complete packaging of the OLED device.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: May 23, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Yawei Liu, Yifan Wang
  • Patent number: 9657404
    Abstract: A method of forming a metallic pattern on a polymer substrate is provided. A mixture layer is formed on a polymer substrate surface. The mixture layer includes an active carrier medium and nanoparticles dispersed in the active carrier medium. A laser process is performed to treat a portion of the mixture layer to form a conductive pattern on the surface of the polymer substrate. A cleaning process is performed to remove an untreated portion of the mixture layer to expose the surface of the polymer substrate, while the conductive pattern is remained on the surface of the polymer substrate. Then, the conductive pattern on the polymer substrate is subjected to an electroplating process to form the metallic pattern over the conductive pattern on the polymer substrate.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: May 23, 2017
    Assignee: Wistron NeWeb Corp.
    Inventors: Babak Radi, Shih-Hong Chen, Yu-Fu Kuo, Tzu-Wen Chuang
  • Patent number: 9653573
    Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: May 16, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Linus Jang, Sivananda K. Kanakasabapathy, Sanjay C. Mehta, Soon-Cheon Seo, Raghavasimhan Sreenivasan
  • Patent number: 9641102
    Abstract: For example, a semiconductor device has a lead connected to a second portion of a chip mounting part on which a semiconductor chip to be a heat source is mounted and a lead connected to a third portion of the chip mounting part on which the semiconductor chip to be the heat source is mounted. Further, each of the leads has a protruding portion protruding from a sealing member. In this manner, it is possible to enhance a heat dissipation characteristic of the semiconductor device.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: May 2, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuhiro Mitamura, Koji Bando, Yukihiro Sato, Takamitsu Kanazawa
  • Patent number: 9634093
    Abstract: A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: April 25, 2017
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Min-Chul Sun, Byung-Gook Park
  • Patent number: 9633998
    Abstract: A semiconductor device is provided. The semiconductor device includes an avalanche photodiode unit and a thyristor unit. The avalanche photodiode unit is configured to receive incident light to generate a trigger current and comprises a wide band-gap semiconductor. The thyristor unit is configured to be activated by the trigger current to an electrically conductive state. A semiconductor device and a method for making a semiconductor device are also presented.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: April 25, 2017
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Stanislav Ivanovich Soloviev, Ahmed Elasser, Alexander Viktorovich Bolotnikov, Alexey Vert, Peter Almern Losee
  • Patent number: 9633852
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: April 25, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ching-Lin Chan, Chen-Yuan Lin, Cheng-chi Lin, Shih-Chin Lien
  • Patent number: 9634211
    Abstract: Each of a plurality of semiconductor light-emitting element has, on an upper surface thereof that has a quadrilateral shape, a pair of connecting portions having different polarities from each other. The pair of connecting portions are aligned on a diagonal of the quadrilateral shape. The diagonal intersects a row direction along which the semiconductor light-emitting elements within a row are arranged. Connecting portions having identical polarity are positioned on an imaginary line parallel to the row direction. Metal wires intersect two sides extending from a corner, on the diagonal, of the upper surface of each of the semiconductor light-emitting elements when viewed from a direction perpendicular to a mounting surface of a substrate for mounting the semiconductor light-emitting elements.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: April 25, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Masumi Abe, Yasufumi Wada, Toshifumi Ogata, Kenji Sugiura
  • Patent number: 9634081
    Abstract: A method for producing a polysilicon resistor device may include: forming a polysilicon layer; implanting first dopant atoms into at least a portion of the polysilicon layer, wherein the first dopant atoms include deep energy level donors; implanting second dopant atoms into said at least a portion of said polysilicon layer; and annealing said at least a portion of said polysilicon layer.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 25, 2017
    Assignee: Infineon Technologies AG
    Inventors: Hermann Gruber, Thomas Gross, Werner Irlbacher, Markus Zundel, Mathias von Borcke, Hans Joachim Schulze
  • Patent number: 9627259
    Abstract: A device manufacturing method according to an embodiment includes forming a film on the second surface side of a substrate having a first surface and the second surface, forming a trench in part of the substrate from the first surface side, while leaving the film to remain, and injecting a substance onto the film from the second surface side, to remove the film at the portion on the second surface side of the trench.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: April 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masamune Takano
  • Patent number: 9627480
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: April 18, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony I. Chou, Judson R. Holt, Arvind Kumar, Henry K. Utomo
  • Patent number: 9613922
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: April 4, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Patent number: 9613984
    Abstract: Provided are a display device, a method of fabricating the display device, and a method of fabricating an image sensor device. The method of fabricating the display device includes preparing a substrate including a cell array area and a peripheral circuit area, forming a silicon layer on the peripheral circuit area of the substrate, forming oxide layers on the cell array area and the peripheral circuit area of the substrate, forming gate dielectric layers on the silicon layer and the oxide layers, forming the gate electrodes on the gate dielectric layers, wherein the gate electrodes expose both ends of the silicon layer and both ends of the oxide layers, and injecting dopant into both ends of the silicon layer and both ends of the oxide layers at the same time.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: April 4, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jong-Heon Yang, Jonghyurk Park, Chunwon Byun, Chi-Sun Hwang
  • Patent number: 9614156
    Abstract: An embodiment of the present invention provides a method for producing a flexible display panel. The method includes the following steps of: providing a bearing substrate and a transparent substrate arranged with the flexible display panel; setting a laser irradiation path and irradiating the bearing substrate by using a laser along the set laser irradiation path to form a mark region on the bearing substrate; placing the flexible display panel on the mark region correspondingly; irradiating from a side of the transparent substrate by re-using the laser along the set laser irradiation path, to peel off the flexible display panel from the transparent substrate; and separating the flexible display panel from the mark region on the bearing substrate to obtain the flexible display panel.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: April 4, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qingrong Ren, Wei Guo
  • Patent number: 9607984
    Abstract: In one embodiment, a common drain semiconductor device includes a substrate, having two transistors integrated therein. The substrate also includes a plurality of active regions on a major surface of the substrate. The active regions of each transistor may be interleaved.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: March 28, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Kazumasa Takenaka, Hidehito Koseki
  • Patent number: 9608161
    Abstract: A semiconductor light-emitting device including an N-type semiconductor layer, a plurality of P-type semiconductor layers, a light-emitting layer, and a contact layer is provided. The light-emitting layer is disposed between the N-type semiconductor layer and the whole of the P-type semiconductor layers. The P-type semiconductor layers are disposed between the contact layer and the light-emitting layer. All the P-type semiconductor layers between the light-emitting layer and the contact layer include aluminum.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: March 28, 2017
    Assignee: PlayNitride Inc.
    Inventors: Shen-Jie Wang, Yu-Chu Li
  • Patent number: 9601440
    Abstract: A method for manufacturing a semiconductor device is disclosed in which the probability of occurrence of a crack is reduced and in which manufacturing cost is also reduced. An exposure mask used in the method is disclosed. Protrusion portions are formed in intersections of scribe lines in an outermost periphery of a scribe line pattern of a surface protection film of the exposure mask, to thereby stick out toward an outer circumference. In this manner, the probability of occurrence of a crack occurring in a device formation section can be reduced so that a reduction in the manufacturing cost can be achieved.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: March 21, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Patent number: 9601648
    Abstract: The present disclosure provides a method of manufacturing a pattern including: forming a trench structure on a substrate using an inkjet method; filling an interior portion of the trench structure with a filler; and removing the trench structure, and a pattern manufactured using the same, and a method of manufacturing a solar battery using the method of manufacturing a pattern and a solar battery manufactured using the same.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: March 21, 2017
    Assignee: LG CHEM, LTD.
    Inventors: Yong-Sung Goo, Joon-Hyung Kim
  • Patent number: 9583375
    Abstract: Methods and systems for forming water soluble masks by dry film lamination are described. Also described are methods of wafer dicing, including formation of a water soluble mask by dry film lamination. In one embodiment, a method involves moisturizing an inner area of a water soluble dry film. The method involves stretching the water soluble dry film over a surface of the semiconductor wafer, and attaching the moistened inner area of the stretched film to the surface of the semiconductor wafer. A method of wafer dicing may further involve patterning the water soluble dry film, exposing regions of the semiconductor wafer between the ICs, and etching the semiconductor wafer through gaps in the patterned water soluble dry film.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: February 28, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, James S. Papanu, Brad Eaton, Ajay Kumar