Abstract: A method for filling a fine hole, having a hole pattern diameter of less than or equal to 0.18 &mgr;m including steps of: (i) filling the fine hole with filler which is obtained by dissolving into an organic solvent a nitrogen-containing compound having mean molecular weight of less than or equal to 800 and containing at least one compound selected from melamine, benzoguanamine, acetoguanamine, glycol-uril, urea, thiourea, guanidine, alkyleneurea and succinylamide, in which hydrogen atoms of amino groups are substituted by at least one hydroxyalkyl group or an alkoxyalkyl groups or both hydroxyalkyl and alkoxyalkyl groups; (ii) drying the filler; and (iii) heating the filler at a temperature of 150-250° C., whereby no bubbles are generated when the fine hole is filled.

Abstract: A method for forming silicide contacts includes forming a layer on silicon-containing active device regions such as source, drain, and gate regions. The layer contains a metal that is capable of forming one or more metal silicides and a material that is soluble in a first metal silicide but not soluble in a second metal silicide, or is more soluble in the first metal silicide than in the second metal silicide. The layer may be formed by vapor deposition methods such as physical vapor deposition, chemical vapor deposition, evaporation, laser ablation, or other deposition method. A method for forming silicide contacts includes forming a metal layer, then implanting the metal layer and/or underlying silicon layer with a material such as that described above. The material may be implanted in the silicon layer prior to formation of the metal layer. Contacts formed include a first metal silicide and a material that is more soluble in a first metal silicide than in a second metal silicide.

Abstract: A method of fabricating a semiconductor package capable of realizing a smaller and more compact size and improving reliability of package product and a fabrication method thereof. A main semiconductor chip operates as a lead frame or a substrate and having a plurality of main chip pads on the outer peripheral part thereof; one or more sub semiconductor chips adhered to a predetermined part of the main semiconductor chip and having a plurality of sub chip pads on the outer peripheral part thereof; an insulating layer formed on the main semiconductor chip in a shape surrounding the sub semiconductor chip to expose the main chip pads and the sub chip pads; a plurality of metal patterns electrically connecting the exposed main chip pad to the sub chip pad or one sub chip pad to another sub chip pad; and a plurality of solder lands formed on a predetermined part of the plurality of metal patterns.

Abstract: A catalyst element remaining in a first semiconductor film subjected to a first heat treatment (crystallization) is moved and concentrated/collected by subjecting a second semiconductor film which is formed on the first semiconductor film and contains a rare gas element to a second heat treatment. That is, the rare gas element is incorporated into the second semiconductor film to generate a strain field as a gettering site.

Abstract: According to one embodiment of the invention, a method is provided. The method includes lining, with a conductive liner, a surface of a dielectric layer. The surface defines at least two trenches separated by a platform. Each of the defined trenches includes a conductor that overlies the conductive liner and is positioned within the each of the defined trenches. The conductor is electrically coupled to the conductive liner. The method also includes covering the portion of the conductive liner overlying the platform after lining the surface. The method also includes removing any uncovered portions of the conductive liner while leaving in place the portion of the conductive liner that was covered.

Abstract: A method for carbon doped oxide (CDO) deposition is described. One method of deposition includes providing a substrate and introducing oxygen to a carbon doped oxide precursor in the presence of the substrate. A carbon doped oxide film is formed on the substrate. In another method the substrate is placed on a susceptor of a chemical vapor deposition apparatus. A background gas is introduced along with the carbon doped oxide precursor and oxygen to form the carbon doped oxide film on the substrate.

Abstract: A method of manufacturing a semiconductor device including providing a first layer, forming a layer of stacked oxide-nitride-oxide layer over the first layer, depositing a first silicon layer over the layer of stacked oxide-nitride-oxide layer, providing a layer of photoresist over the first silicon layer, patterning and defining the photoresist layer, etching the first silicon layer and stacked oxide-nitride-oxide layer unmasked by the photoresist, removing the photoresist layer, providing a cleaning solution to the stacked oxide-nitride-oxide layer with the first silicon layer as a mask, and depositing a second layer of polysilicon over the first silicon layer to form a combined silicon layer.

Abstract: A method of forming a bond pad structure reinforced with insulator spacers located on the sides of the bond pad structure has been developed. The method features formation of an aluminum based bond pad structure located overlying and contacting a top portion of a metal interconnect structure exposed in an opening in an intermetal dielectric layer. After deposition of an insulator layer such as silicon nitride or silicon oxide, an anisotropic dry etch procedure is employed to define the insulator spacers on the sides of the bond pad structure. The presence of insulator spacers on the sides of the bond pad structure reduces the risk of bond pad damage which can occur during subsequent pre-wire bonding dicing and transportation procedures.

Abstract: Techniques of shallow trench isolation and devices produced therefrom are shown. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device. The shallow trench isolation structures are used on a variety of substrates including silicon-on-insulator (SOI) substrates and silicon-on-nothing (SON) substrates.

Abstract: The present invention relates to metal interconnections for bit lines having a low resistance and an advanced morphology and a method of forming the same including: forming an inter-layer insulation film on a semiconductor substrate, the inter-layer insulation film containing a contact hole for the bit line; forming a plug within the contact hole; forming a barrier metal defined on the plug; and forming a bit line on the inter-layer insulation film.

Abstract: A method of manufacturing semiconductor devices. A gate structure is formed over a substrate. A dopant implantation is carried out to form a lightly doped region in the substrate on each side of the gate structure. An insulation layer is formed over the substrate. A portion of the insulation is later removed so that a portion of the insulation layer is retained over the substrate on each side of the gate structure. A spacer is formed on each sidewall of the gate structure. Another ion implantation is carried out such that the dopants penetrate through the insulation layer on the substrate on each side of the gate structure to form a heavily doped region in the substrate.

Abstract: A method of manufacturing a semiconductor device etches a feature on a substrate in accordance with a photoresist mask. The photoresist mask is removed by plasma etching. Laser thermal annealing is performed to vaporize polymer residue created during the stripping of the photoresist mask, and to repair damage to the substrate.

Abstract: In a stand-alone snapback NMOS ESD protection structure method of manufacturing, the breakdown voltage is reduced and the structure is made more resilient to hot carrier and soft leakage degradation in the gate region by blocking the NLDD and partially blocking the n+ drain region between the gate and drain region.

Abstract: A method for fabricating a capacitor that prevents etching solution from attacking an inter-layer deposition layer in wet-etching an oxide which supports bottom electrodes.

Abstract: A sole state imaging device includes a photodetection diode and an insulated gate field effect transistor provided adjacent to the photodetection diode for optical signal detection. In a method of making the device, a carrier pocket is formed in a second well region, and an element isolation insulating film is formed to isolate adjacent unit pixels from each other. In addition, an element isolation region of an opposite conductivity type is formed to isolate a second semiconductor layer of one conductivity type in such a way as to include the lower surface of the element isolation insulating film and reach a first semiconductor layer.

Abstract: A method for fabricating a Group III nitride film is provided, including the steps of preparing a substrate, forming an underfilm and then forming the Group III nitride film on the underfilm. The underfilm is a Group III nitride comprising at least one Group III element and includes at least 50 atomic percent of elemental Al with respect to all of the Group III elements of the Group III nitride of the underfilm. The surface of the underfilm is contoured (concave-convex) and includes flat regions, and less than 50% of the underfilm surface is occupied by the flat regions.

Abstract: In a semiconductor device manufacturing method in which a package including a semiconductor chip is mounted on a wiring board via tape ball grid array (TBGA), a tape base material having a device hole and a plurality of leads is provided with one end of the leads extended inside the device hole and a part of the other end of the leads forming lands for connecting bump electrodes. The semiconductor chip is arranged in the device hole of the tape base material to electrically connect the semiconductor chip and the one end of the leads. A sealing resin and reinforcing frame surrounding the periphery of the sealing resin are monolithically formed by transfer molding. The tape base material is fixed in an area between the semiconductor chip and the reinforcing frame by a lower mold and a projection of an upper mold.

Abstract: A method for manufacturing a thermoelectric cooling mechanism for an integrated circuit is disclosed. Initially, electric circuits are formed on one side of a wafer. Subsequently, thermoelectric cooling devices are formed on an opposite side of the same wafer. Specifically, the thermoelectric cooling devices are formed by depositing a first conductive layer, depositing a layer of Peltier material on top of the first conductive layer, building a set of N30 regions and P30 regions within the Peltier material layer, and depositing a second conductive layer on top of the Peltier material layer.

Abstract: A method of fabricating flash memory cell is described. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer; forming a buffer layer; removing portions of the buffer layer to farm a floating gate insulating layer; forming a second conductive layer; removing portions of the first conductive layer and the second conductive layer, such that the second conductive layer forms conductive spacers having conductive tips situated at the tips, and the floating gate insulating layer, the floating gate and the first gate insulating layer are combined as a floating gate region; forming a second insulating layer; forming a third conductive layer; removing portions of the third conductive layer and the second insulating layer to form a control gate, a second gate insulating layer, a first opening and a second opening; forming a source region on the substrate; forming spacers; and forming a drain region on the substrate.

Abstract: The invention is a semiconductor optical device and method of fabrication where the device includes an active region with an active layer having a first index of refraction, and a blocking region having a second, lower index of refraction. A semiconductor layer having an index of refraction higher than the blocking region is formed over both the active and blocking regions so that the semiconductor layer is in closer proximity to the active layer in areas not covered by the blocking region so as to decrease the difference between the effective index of refraction in the active region and the effective refractive index of the blocking region. Such devices are particularly useful for pumping optical amplifiers since greater power can be achieved while maintaining single mode emission.