Abstract: A competitive, simple, single-substrate wafer-level packaging technique capable of creating a vacuum-sealed protective cavity around moving or other particular components of a MEMS is described. The technique uses common semiconductor materials, processing steps and equipment to provide a stable vacuum environment of, for example less than 1 Pa, in a sealed cavity. The environment protects components of the MEMS against micro-contamination from particles and slurry of a waver dicing process and against fluctuations of atmospheric condition to ensure long term reliability.

Abstract: The trench-isolation structures for fabricating semiconductor devices using two different multilayer masking structures are disclosed by the present invention, in which the extended buffer spacers located in the isolation regions are formed on the sidewalls of two different multilayer masking structures having a masking dielectric layer on a pad-oxide layer and a masking dielectric layer on a conductive layer over a gate-oxide layer. The extended buffer spacers not only act as the etching mask for forming the trenches in the semiconductor substrate but also play significant roles for obtaining high-reliability and high-efficiency trench isolation of the present invention. The first role of the extended buffer spacers of the present invention is to offer the buffer regions for preventing the bird's beak formation around the edge of the active region during the thermal oxidation of the trench surface, so that the active area used to fabricate the active device is not sacrificed.

Abstract: A method for making trench DMOS is provided that improves the breakdown voltage of the oxide layer in a device having at least a first trench disposed in the active region of the device and a second trench disposed in the termination region of the device. In accordance with the method, mask techniques are used to thicken the oxide layer in the vicinity of the top corner of the second trench, thereby compensating for the thinning of this region (and the accompanying reduction in breakdown voltage) that occurs due to the two-dimensional oxidation during the manufacturing process.

Abstract: A method of using dichloroethene and ammonia to provide chlorine and nitrogen during the growth of an in-situ hardened gate dielectric. The method provides a gaseous source of gettering agent and a gaseous source of dielectric strengthening agent that are compatible with each other and can be used during the formation of in-situ hardened dielectric or the strengthening of an already formed dielectric.

Abstract: In one aspect, a method of forming an electronic device includes forming a layer of undoped oxide over a layer of doped oxide. A first electrode is formed proximate thereto. With the undoped oxide layer being outwardly exposed, a silicon nitride layer is formed on the undoped oxide layer and over the first electrode by low pressure chemical vapor deposition to a thickness of no greater than 80 Angstroms. The substrate is exposed to oxidizing conditions of at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride on the undoped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed, over the silicon dioxide layer and the first electrode. Other aspects are contemplated.

Abstract: A method of fabricating a flash memory device uses a self-aligned non-exposure pattern formation process. A conductive layer and an oxidation-blocking layer are formed on a stepped pattern including a floating gate pattern and an inter-gate insulating layer pattern such that the conductive layer and the oxidation-blocking layer conform to the stepped pattern. A photoresist layer is formed on the oxidation-blocking layer such that the photoresist layer has an upper surface situated above the oxidation-blocking layer. A portion of the photoresist layer is dissolved, without having photo-exposed the photoresist layer, by soaking the photoresist layer in developing solution. This soaking alone, or supplemented with an etch back process, is carried out until the upper surface of the photoresist layer is situated below the upper surface of the oxidation-blocking layer on the stepped pattern. The resulting photoresist pattern exposes that part of the oxidation-blocking layer on the stepped pattern.

Abstract: A method of forming electric wiring using a dual damascene process wherein prevention of damage to a lower conductive pattern and low contact resistance may be achieved. A first insulation layer having a first trench filled with a conductive material is formed on a semiconductor substrate. A first etch stop layer, a second insulation layer and a third insulation layer are sequentially formed thereon. A capping layer is formed on the third insulation layer. A via hole is formed by selectively etching the capping layer, third insulation layer and second insulation layer. Then the capping layer is partially etched and a polymer layer is formed on the exposed first etch stop layer. A second trench is formed and the electric wiring is formed by filling a conductive material in a resulting structure. The polymer layer prevents damage to the conductive pattern by protecting the first etch stop layer.

Abstract: A process for forming high k dielectric thin films on a substrate, e.g., silicon, by 1) low temperature (500° C. or less) deposition of a dielectric material onto a surface, followed by 2) high temperature post-deposition annealing. The deposition can take place in an oxidative environment, followed by annealing, or alternatively the deposition can take place in a non-oxidative environment (e.g., N2), followed by oxidation and annealing.

Abstract: An integrated circuit is made with transistors having varying characteristics in the same well. One transistor, which is particularly useful as an I/O device, has a relatively deep source/drain with a relatively thick gate dielectric. The well doping is selected so that this transistor has low leakage. Another transistor type, which is particularly useful for low voltage analog purposes, has a relatively thin gate dielectric and the relatively deep source/drain. A third transistor type, which is particularly suited for high density and low power operation, has a relatively shallow source/drain, the relatively thin gate dielectric, and a high dose halo implant. A fourth transistor type, which may also be present for high-speed operations, has the relatively thin gate dielectric, the relatively shallow source/drain, and may have a halo implant. The halo implant will be of a lower dosage than the halo implant for the third transistor type.

Abstract: A method of forming bumped substrates with protuberances for inverted or flip-connection bonding of electronic devices including semiconductor devices, integrated circuits, and/or application specific integrated circuits and electromechanical devices. The substrates are high temperature insulating materials provided with a conductive pattern. The conductive pattern has contact areas corresponding to the input/output (I/O) pads of the electronic device. A metal is applied over the contact areas, and the temperature is raised above the melting point of the metal causing the metal to melt and draw back into a convex protuberance over the contact areas. The convex protuberances are suitable for connecting to the electronic devices by conductive adhesive bonding or metallurgically bonding such as thermocompression, thermosonic or ultrasonic bonding.

Abstract: A semiconductor device having a P type well region formed inside a P type semiconductor substrate, on which at least three gate insulating films each having a different thickness are formed. Also, the device has the gate electrode formed extending over the three gate insulating films. The ion implantation of the impurity for controlling the threshold voltage is performed only under the thinnest gate insulating film of the three gate insulating films.

Abstract: A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a second heavily-doped P-type area separate from the second area; forming at the periphery of this second area a third N-type area; forming by epitaxy a second silicon layer; forming a deep trench crossing the first and second silicon layers, penetrating into the substrate and laterally separating the second area from the third area; and performing an anneal such that the dopant of the third area is in continuity with that of the first area.

Abstract: A method for bonding an IC chip by a non-conductive adhesive that contains between about 5 weight % and about 25 weight % of a non-conductive filler is described. The filler particles in the filler material must have a hardness that is higher, and preferably at least two times higher, than the metal material forming the bump. Moreover, the filler particles must be non-electrically conductive such that electrical shorts between a plurality of bumps on the IC chip do not occur. The concentration of the filler in the adhesive must be high enough so as to reduce the CTE of the adhesive to match that of the IC chip and the substrate, and low enough so as not to impede the electrical communication between the bumps on the IC chip and the bond pads on the substrate.

Abstract: A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. The ozone delivery is pulsed on and off. Optionally, the delivery of the ozone and the delivery of the TEOS are pulsed on and off alternately.

Abstract: A method for reducing microsteps on an epitaxial layer deposited on a polished semiconductor wafer substrate by post-epitaxial thermal oxidation. The method produces very smooth semiconductor wafers by performing the steps of depositing an epitaxial layer on a wafer substrate, oxidizing a top portion of the expitaxial layer, and removing the oxidized top portion. As a result, the wafer's surface presents little or no microsteps thereon.

Abstract: A stacked-gate flash memory cell includes a trench formed in a substrate and a tunneling oxide layer formed on the substrate. A first part of the floating gate is formed on the tunneling oxide layer. A protruding isolation filler is formed in the trench and protrudes over the upper surface of the first part of the floating gate, thereby forming a cavity between the two adjacent raised isolation structures. A second part of the floating gate is formed of HSG-Si over the surface of the cavity to have a U-shaped structure in cross sectional view. A dielectric layer is conformably formed on the surface of the second part of the floating gate and the isolation structures, and a control gate is formed on the dielectric layer.

Abstract: The method for fabricating a semiconductor device in accordance with the present invention has the steps of: forming a metal film as a lower electrode of a capacitor on a semiconductor substrate, followed by forming a capacity insulator film over the lower electrode by the ALCVD process; and forming an upper electrode of the capacitor on the capacity insulator film.

Abstract: A method is provided for well printing a specified pattern even when the exposure treatment using a resist mask uses exposure light with a wavelength over 200 nm. When exposure treatment is applied to a semiconductor wafer by using exposure light with a wavelength over 200 nm, a photomask is used. The photomask is provided with an opaque pattern of a resist layer on an organic layer which is photoabsorptive in reaction to exposure light.

Abstract: A method for forming a silicon carbide layer for use in integrated circuit fabrication is disclosed. The silicon carbide layer is formed by reacting a gas mixture of a silicon source, a carbon source, and an inert gas in the presence of an electric field. The electric field is generated using mixed frequency radio frequency (RE) power. The silicon carbide layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the silicon carbide layer is used as a hardmask for fabricating integrated circuit structures such as, for example, a damascene structure. In another integrated circuit fabrication process, the silicon carbide layer is used as an anti-reflective coating (ARC) for DUV lithography.

Abstract: A process for manufacturing a semiconductor memory device comprises the steps of: (a) forming a tunnel oxide film, a first (1st) conductive film to be a lower floating gate, a 1st insulating film and a second (2nd) insulating film in this order on a semiconductor substrate and patterning the 2nd insulating film, the 1st insulating film, the 1st conductive film and the tunnel oxide film into a desired configuration; (b) forming a third (3rd) insulating film on the entire surface of the resulting substrate; (c) reducing the 3rd insulating film until the 2nd insulating film is exposed; (d) removing the 2nd insulating film; (e) removing the 1st insulating film while further reducing the 3rd insulating film; (f) forming a 2nd conductive film to be an upper floating gate on the 1st conductive film and the 3rd insulating film; (g) flattening the 2nd conductive film until the 3rd insulating film is exposed; and (h) forming an interlayer capacitance film and a 3rd conductive film to be a control gate on the 2nd conduc